NDLI: Automatic generation of functional models for embedded processor extensions

Please wait, while we are loading the content...

The mobile society: chances and challenges for micro- and power electronics

Automated generation of directed tests for transition coverage in cache coherence protocols

CACTI-3DD: architecture-level modeling for 3D die-stacked DRAM main memory

Using timing analysis for the design of future switched based ethernet automotive networks

IR-drop analysis of graphene-based power distribution networks

Fast and lightweight support for nested parallelism on cluster-based embedded many-cores

EDA solutions to new-defect detection in advanced process technologies

Beyond CMOS: benchmarking for future technologies

Accurately timed transaction level models for virtual prototyping at high abstraction level

Guidelines for model based systems engineering

Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems

Playing games with scenario- and resource-aware SDF graphs through policy iteration

NBTI mitigation by optimized NOP assignment and insertion

Experimentally driven verification of synthetic biological circuits

Fast cycle estimation methodology for instruction-level emulator

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

Middleware services for network interoperability in smart energy efficient buildings

Variation-aware leakage power model extraction for system-level hierarchical power analysis

State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systems

Hybrid source-level simulation of data caches using abstract cache models

RTL analysis and modifications for improving at-speed test

Embedded systems and software challenges in electric vehicles

Accelerators and emulators: can they become the platform of choice for hardware verification?

A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoring

Energy-efficient branch prediction with compiler-guided history stack

PCASA: probabilistic control-adjusted selective allocation for shared caches

Preemption delay analysis for floating non-preemptive region scheduling

Error patterns in MLC NAND flash memory: measurement, characterization, and analysis

Worst-case delay analysis of variable bit-rate flows in network-on-chip with aggregate scheduling

Research and innovation on advanced computing: an EU Perspective

Memristor technology in future electronic system design

TempoMP: integrated prediction and management of temperature in heterogeneous MPSoCs

A guiding coverage metric for formal verification

Optimizing performance analysis for synchronous dataflow graphs with shared resources

Model checking of scenario-aware dataflow with CADP

Design for test and reliability in ultimate CMOS

Optimal energy management and recovery for FEV

Virtual platforms: breaking new grounds

An FPGA-based accelerator for cortical object classification

A SAT-based fitness function for evolutionary optimization of polymorphic circuits

Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters

Design of streaming applications on MPSoCs using abstract clocks

Test pin count reduction for NoC-based test delivery in multicore SOCs

Timing modeling with AUTOSAR: current state and future directions

QBF-based boolean function Bi-decomposition

Complexity, quality and robustness - the challenges of tomorrow's automotive electronics

Panel: what is EDA doing for trailing edge technologies?

Reli: hardware/software checkpoint and recovery scheme for embedded processors

Efficient gröbner basis reductions for formal verification of galois field multipliers

Transistor-level gate model based statistical timing analysis considering correlations

Robust and flexible mapping for real-time distributed applications during the early design phases

Logic encryption: a fault analysis perspective

Batteries and battery management systems for electric vehicles

Power management of multi-core chips: challenges and pitfalls

SAFER PATH: security architecture using fragmented execution and replication for protection against trojaned hardware

Combining module selection and replication for throughput-driven streaming programs

Automatic design of low-power encoders using reversible circuit synthesis

Automated construction of a cycle-approximate transaction level model of a memory controller

An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

ITRS 2011 analog EDA challenges and approaches

Pathways to servers of the future: highly adaptive energy efficient computing (HAEC)

Amplitude demodulation-based EM analysis of different RSA implementations

3DHLS: incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

An efficient framework for passive compact dynamical modeling of multiport linear systems

Time-triggered implementations of mixed-criticality automotive software

Input vector monitoring on line concurrent BIST based on multilevel decoding logic

Moore meets Maxwell

Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs

A TDM NoC supporting QoS, multicast, and fast connection set-up

Spintronic memristor based temperature sensor design with CMOS current reference

Comparative analysis of SRAM memories used as PUF primitives

Towards improving simulation of analog circuits using model order reduction

Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique

VLSI legalization with minimum perturbation by iterative augmentation

Programmability and performance portability aspects of heterogeneous multi-/manycore systems

Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC

Towards a wireless medical smart card

A fast, source-synchronous ring-based network-on-chip design

Modeling and design exploration of FBDRAM as on-chip memory

A network-on-chip-based turbo/LDPC decoder architecture

Selective flexibility: breaking the rigidity of datapath merging

Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction

On effective flip-chip routing via pseudo single redistribution layer

Advances in variation-aware modeling, verification, and testing of analog ICs

New foundry models - accelerations in transformations of the semiconductor industry

On ESL verification of memory consistency for system-on-chip multiprocessing

TagTM - accelerating STMs with hardware tags for fast meta-data access

Fair energy resource allocation by minority game algorithm for smart buildings

Off-path leakage power aware routing for SRAM-based FPGAs

A divide and conquer based distributed run-time mapping methodology for many-core platforms

Out-of-order parallel simulation for ESL design

SURF algorithm in FPGA: a novel architecture for high demanding industrial applications

Benefits of green energy and proportionality in high speed wide area networks connecting data centers

Verifying timing synchronization constraints in distributed embedded architectures

An accurate single event effect digital design flow for reliable system level design

Genetic/bio design automation for (re-)engineering biological systems

Verification coverage of embedded multicore applications

An MILP-based aging-aware routing algorithm for NoCs

Low-power embedded system for real-time correction of fish-eye automotive cameras

Runtime power estimator calibration for high-performance microprocessors

Accurate source-level simulation of embedded software with respect to compiler optimizations

Test generation for clock-domain crossing faults in integrated circuits

Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals

Toward virtualizing branch direction prediction

Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores

Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform

Modeling and testing of interference faults in the nano NAND flash memory

Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches

Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation

Verification of partial designs using incremental QBF solving

Compositional system-level design exploration with planning of high-level synthesis

An instruction scratchpad memory allocation for the precision timed architecture

Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding

Mach-zehnder interferometer based design of all optical reversible binary adder

Holistic modeling of embedded systems with multi-discipline Feedback: application to a precollision mitigation braking system

SPDF: a schedulable parametric data-flow MoC

On effective TSV repair for 3D-stacked ICs

Challenges and new trends in probabilistic timing analysis

Automatic transition between structural system views in a safety relevant embedded systems development process

Measuring and improving the robustness of automotive smart power microelectronics

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Scalable progress verification in credit-based flow-control systems

Current source modeling for power and timing analysis at different supply voltages

A methodology for automated design of hard-real-time embedded streaming systems

Low-cost implementations of on-the-fly tests for random number generators

P2012: building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

ASIC implementations of five SHA-3 finalists

Exploiting area/delay tradeoffs in high-level synthesis

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM

Refinement of UML/MARTE models for the design of networked embedded systems

Testing RF circuits with true non-intrusive built-in sensors

CrashTest'ing SWAT: accurate, gate-level evaluation of symptom-based resiliency solutions

UWB: innovative architectures enable disruptive low power wireless applications

RSM: a small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs

Multi-token resource sharing for pipelined asynchronous systems

Analysis and design of sub-harmonically injection locked oscillators

Timing analysis of cyber-physical applications for hybrid communication protocols

High performance reliable variable latency carry select addition

Parallel probing: dynamic and constant time setup procedure in circuit switching NoC

3D-FlashMap: a physical-location-aware block mapping strategy for 3D NAND flash memory

Comparison of self-timed ring and inverter ring oscillators as entropy sources in FPGAs

Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

State-based full predication for low power coarse-grained reconfigurable architecture

Agglomerative-based flip-flop merging with signal wirelength optimization

Verifying jitter in an analog and mixed signal design using dynamic time warping

Area efficient asynchronous SDM routers using 2-stage clos switches

Bloom filter-based dynamic wear leveling for phase-change RAM

A complexity adaptive channel estimator for low power

An out-of-order superscalar processor on FPGA: the ReOrder buffer design

Almost every wire is removable: a modeling and solution for removing any circuit wire

AIR (aerial image retargeting): a novel technique for in-fab automatic model-based retargeting-for-yield

Generating instruction streams using abstract CSP

Dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design

On demand dependent deactivation of automotive ECUs

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

Dual greedy: adaptive garbage collection for page-mapping solid-state disks

A probabilistic analysis method for functional qualification under mutation analysis

NOCEVE: network on chip emulation and verification environment

Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer

Task implementation of synchronous finite state machines

Cross entropy minimization for efficient estimation of SRAM failure rate

Hazard driven test generation for SMT processors

AFRA: a low cost high performance reliable routing for 3D mesh NoCs

Mechatronic system for energy efficiency in bus transport

Estimation based power and supply voltage management for future RF-powered multi-core smart cards

Scheduling for register file energy minimization in explicit datapath architectures

A new SBST algorithm for testing the register file of VLIW processors

A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system

S/DC: a storage and energy efficient data prefetcher

Dynamic cache management in multi-core architectures through run-time adaptation

Static scheduling of a time-triggered network-on-chip based on SMT solving

Impact of resistive-open defects on the heat current of TAS-MRAM architectures

Low power aging-aware register file design by duty cycle balancing

Statistical thermal modeling and optimization considering leakage power variations

Non-solution implications using reverse domination in a modern SAT-based debugging environment

Correct-by-construction multi-component SoC design

Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs

Towards accurate hardware stereo correspondence: a real-time FPGA implementation of a segmentation-based adaptive support weight algorithm

Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switches

Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection

Modeling static-order schedules in synchronous dataflow graphs

DfT schemes for resistive open defects in RRAMs

Towards new applications of multi-function logic: image multi-filtering

A resilient architecture for low latency communication in shared-L1 processor clusters

Formal methods for ranking counterexamples through assumption mining

Clock skew scheduling for timing speculation

Co-design techniques for distributed real-time embedded systems with communication security constraints

Post-deployment trust evaluation in wireless cryptographic ICs

Multi-core architecture design for ultra-low-power wearable health monitoring systems

Side channel analysis of the SHA-3 finalists

Predicting best design trade-offs: a case study in processor customization

Sliding-mode control to compensate PVT variations in dual core systems

Debugging of inconsistent UML/OCL models

Monitoring active filters under automotive aging scenarios with embedded instrument

A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems

Revealing side-channel issues of complex circuits by enhanced leakage models

Design of low-complexity digital finite impulse response filters on FPGAs

Design of an intrinsically-linear double-VCO-based ADC with $2^{nd}-order$ noise shaping

A cyberphysical synthesis approach for error recovery in digital microfluidic biochips

Salvaging chips with caches beyond repair

A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels

Asymmetry of MTJ switching and its implication to STT-RAM designs

A sensor-assisted self-authentication framework for hardware trojan detection

A GPU-accelerated envelope-following method for switching power converter simulation

UPaRC: ultra-fast power-aware reconfiguration controller

Fixed origin corner square inspection layout regularity metric

MEDS: mockup electronic data sheets for automated testing of cyber-physical systems using digital mockups

Power-efficient calibration and reconfiguration for on-chip optical communication

A compression-based area-efficient recovery architecture for nonvolatile processors

A high performance split-radix FFT with constant geometry architecture

Partial online-synthesis for mixed-grained reconfigurable architectures

Mapping into LUT structures

Layout-driven robustness analysis for misaligned carbon nanotubes in CNTFET-based standard cells

A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture

DRAM selection and configuration for real-time mobile systems

Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks

Post-synthesis leakage power minimization

Approximating checkers for simulation acceleration

Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks

Neighbor-aware dynamic thermal management for multi-core platform

Enabling dynamic assertion-based verification of embedded software through model-driven design

Extending the lifetime of NAND flash memory by salvaging bad blocks

Intelligent and collaborative embedded computing in automation engineering

Application-specific memory partitioning for joint energy and lifetime optimization

Multi-objective aware extraction of task-level parallelism using genetic algorithms

On the optimality of K longest path generation algorithm under memory constraints

An architecture-level approach for mitigating the impact of process variations on extensible processors

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs

Formal analysis of sporadic overload in real-time systems

PowerAdviser: an RTL power platform for interactive sequential optimizations

Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency

Time analysable synchronisation techniques for parallelised hard real-time applications

An FPGA-based parallel processor for black-scholes option pricing using finite differences schemes

A fast analog circuit yield estimation method for medium and high dimensional problems

Design space pruning through hybrid analysis in system-level design space exploration

Memory-map selection for firm real-time SDRAM controllers

Performance-reliability tradeoff analysis for multithreaded applications

Reducing the energy cost of computing through efficient co-scheduling of parallel workloads

MAPG: memory access power gating

Probabilistic response time bound for CAN messages with arbitrary deadlines

Large signal simulation of integrated inductors on semi-conducting substrates

Predictive control of networked control systems over differentiated services lossy networks

Mitigating lifetime underestimation: a system-level approach considering temperature variations and correlations between failure mechanisms

Simulation of the steady state of oscillators in the time domain

Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

Component-based and aspect-oriented methodology and tool for real-time embedded control systems design

Congestion-aware scheduling for NoC-based reconfigurable systems

Row-shift decompositions for index generation functions

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

Challenges in verifying an integrated 3D design

A case study on the application of real phase-change RAM to main memory subsystem

Towards parallel execution of IEC 61131 industrial cyber-physical systems applications

Fast isomorphism testing for a graph-based analog circuit synthesis framework

Real-time implementation and performance optimization of 3D sound localization on GPUs

State of health aware charge management in hybrid electrical energy storage systems

Exploring pausible clocking based GALS design for 40-nm system integration

Cyber-physical cloud computing: the binding and migration problem

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations

A high-performance dense block matching solution for automotive 6D-vision

A scan pattern debugger for partial scan industrial designs

Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors

Static analysis of asynchronous clock domain crossings

An adaptive approach for online fault management in many-core architectures

Optimization intensive energy harvesting

FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs

Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric

A scalable GPU-based approach to accelerate the multiple-choice knapsack problem

An hybrid architecture to detect transient faults in microprocessors: an experimental validation

Designing FlexRay-based automotive architectures: a holistic OEM approach

Exploiting binary translation for fast ASIP design space exploration on fpgas

Voltage propagation method for 3-D power grid analysis

Enhancing non-linear kernels by an optimized memory hierarchy in a high level synthesis flow

Evaluation of a new RFID system performance monitoring approach

Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems

Design of a low-energy data processing architecture for WSN nodes

Yield optimization for radio frequency receiver at system level

Workload-aware voltage regulator optimization for power efficient multi-core processors

A framework for simulating hybrid MTJ/CMOS circuits: atoms to system approach

VaMV: variability-aware memory virtualization

Application-specific power-efficient approach for reducing register file vulnerability

Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach

An energy efficient DRAM subsystem for 3D integrated SoCs

A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems

Hybrid simulation for extensible processor cores

On-line scheduling of target sensitive periodic tasks with the gravitational task model

Automated critical device identification for configurable analogue transistors

Eliminating invariants in UML/OCL models

Architecting a common-source-line array for bipolar non-volatile memory devices

Leveraging reconfigurability to raise productivity in FPGA functional debug

Online scheduling for multi-core shared reconfigurable fabric

Analysis of multi-domain scenarios for optimized dynamic power management strategies

On-chip source synchronous interface timing test scheme with calibration

Layout-aware optimization of STT MRAMs

MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded systems evolution

SCFIT: a FPGA-based fault injection technique for SEU fault model

PUF-based secure test wrapper design for cryptographic SoC testing

Characterization of the bistable ring PUF

Run-time power-gating in caches of GPUs for leakage energy savings

An operational matrix-based algorithm for simulating linear and fractional differential circuits

Automatic generation of functional models for embedded processor extensions

A flexible and fast software implementation of the FFT on the BPE platform

An integrated test generation tool for enhanced coverage of simulink/stateflow models

Hierarchical propagation of geometric constraints for full-custom physical design of ICs

Model driven resource usage simulation for critical embedded systems

Double-patterning friendly grid-based detailed routing with online conflict resolution

RAG: an efficient reliability analysis of logic circuits on graphics processing units

Design and analysis of via-configurable routing fabrics for structured ASICs

Automatic generation of functional models for embedded processor extensions

Content Provider	ACM Digital Library
Author	Sun, Fei
Abstract	Early architectural exploration and design validation are becoming increasingly important for multi-processor systems-on-chip (MPSoC) designs. Native functional simulations can provide orders of magnitude in speedup over cycle or instruction level simulations but often require dedicated maintenance. In this work, we present a tool called NATIVESIM to automatically generate the functional models for embedded processor extensions. We provide a mechanism to address the challenge of modeling a subset of the processor architecture, with no visibility to the rest of the processor. We illustrate the problem of modeling the processor extensions when the endianness of the target processor is different from the host system and provide a solution to it. Experiments on several benchmark programs indicate that native execution of the target application with the functional models of the processor extensions can achieve large simulation run-time speedup over simulations based on either cycle accurate models (up to 14102x with an average of 3924x) or compiled functional models of an entire processor (up to 103x with an average of 31.6x).
Starting Page	304
Ending Page	307
Page Count	4
File Format	PDF
ISBN	9783981080186
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-03-12
Publisher Place	San Jose
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in