NDLI: Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache

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System perspective on embedded multimedia

A whole layer performance analysis method for Android platforms

Support of software framework for embedded multi-core systems with Android environments

Scheduling of stream programs onto SPM enhanced processors with code overlay

Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache

A flash-friendly $B^{+}-tree$ with endurance-awareness

On the management of multichannel architectures of solid-state disks

Shadow-based vehicle model refinement and tracking in advanced automotive driver assistance systems

Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos

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Automatic derivation of polyhedral process networks from while-loop affine programs

A greedy approach to tolerate defect cores for multimedia applications

Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?

Tractable real-time schedulability analysis for mode changes under temporal isolation

Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware

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Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache

Content Provider	IEEE Xplore Digital Library
Author	Jianhua Li Liang Shi Xue, C.J. Chengmo Yang Yinlong Xu
Copyright Year	2011
Description	Author affiliation: Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong (Jianhua Li; Liang Shi; Xue, C.J.) \|\| Department of Electrical & Computer Engineering, University of Delaware, USA (Chengmo Yang) \|\| College of Computer Science & Technology, University of Science & Technology of China, China (Yinlong Xu)
Abstract	Hybrid cache architectures have been proposed to mitigate the increasing on-chip power dissipation through the exploitation of the emerging non-volatile memories (NVMs). To overcome the high energy and long latency associated with write operations of NVMs, a small SRAM is typically incorporated into the hybrid cache for accommodating write-intensive cache blocks. How to efficiently manage this SRAM and manipulate the write operations are crucial to the performance of the hybrid cache. In this paper, we first present our observation that the intensity of write operations on different cache sets is usually non-uniform for real applications, such as multimedia, multi-programmed, multithreaded applications. The previously proposed hybrid cache schemes can not efficiently and symmetrically utilize the small SRAM to accommodate such widely-existing non-uniform writes on cache sets. Based on this observation, we propose a novel hybrid cache design, Dual Associative Hybrid Cache (denoted as DAHYC), as well as the corresponding cache management policy. By organizing the SRAM blocks in the hybrid cache as a semi-independent set-associative cache, several hybrid cache sets can efficiently share and cooperatively utilize their SRAM blocks, instead of exclusively utilizing the SRAM blocks in each cache set in previous hybrid cache schemes, to boost power-efficiency. Through prudently manipulating the locality information of SRAM blocks in both the NVM sets and the SRAM sets, the proposed cache management policy also delivers high-performance. Experimental results show that, compared with previous works, the DAHYC can reduce the dynamic power of the hybrid cache by 24.8% on average and up to 54% for SPEC2000 INT benchmarks, while at the same time improving the performance of the hybrid cache by 1.16% on average.
Starting Page	19
Ending Page	28
File Size	933548
Page Count	10
File Format	PDF
ISBN	9781457721236
e-ISBN	9781457721229
DOI	10.1109/ESTIMedia.2011.6088521
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-13
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy Efficient Non-Volatile Memory Write Non-Uniformity Hybrid Cache
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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