NDLI: Approximating checkers for simulation acceleration

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Approximating checkers for simulation acceleration

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Approximating checkers for simulation acceleration

Content Provider	ACM Digital Library
Author	Nahir, Amir Mammo, Biruk Bertacco, Valeria Chatterjee, Debapriya Morad, Ronny Pidan, Dmitry Ziv, Avi
Abstract	Simulation-based functional verification is the key validation methodology the industry. The performance of logic simulators, however, is not sufficient to attain acceptable verification coverage on large industrial designs within the time-frame available. Acceleration platforms are a valuable addition to the verification effort in that they can provide much higher coverage in less time. Unfortunately, these platforms do not provide the rich checking capability of software-based simulation. We propose a novel solution to deploy those complex checkers, typical of simulation-based environments, onto acceleration platforms. To this end, checkers must be transformed into synthesizable, compact logic blocks with bug-detection capabilities similar to that of their software counterparts. Our "approximate checkers" trade off logic complexity with bug detection accuracy by leveraging novel techniques to approximate complex software checkers into small synthesizable hardware blocks, which can be simulated along with the design on an acceleration platform. We present a general checker taxonomy, propose a range of approximation techniques based on a checker's characteristic and provide metrics for evaluating its bug detection capabilities.
Starting Page	153
Ending Page	158
Page Count	6
File Format	PDF
ISBN	9783981080186
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-03-12
Publisher Place	San Jose
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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