NDLI: A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

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A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

Content Provider	ACM Digital Library
Author	Baghini, Maryam Shojaei Dave, Marshnil Vipin Sharma, Dinesh Kumar
Abstract	Current mode signaling(CMS) scheme is one of the promising alternatives to voltage mode buffer insertion scheme for high-speed low-power data transmission over long on-chip interconnects. In this paper we present a CMS scheme with dynamic overdriving driver (DOD) whose performance is robust against intra-die and inter-die process variations. We show that throughput of the CMS scheme proposed in [1] degrades by 33% in the presence of intra-die process variations whereas that of the scheme in [2] degrades by 36% in the worst case process corner. Simulation results show that throughput of the proposed CMS scheme degrades by only 9.5% in presence of intra-die process variations and 22% in the worst case process corner. In this process corner, logic speed itself degrades by 23% and hence 22% of throughput degradation of the proposed signaling scheme is not a major concern. In the typical process corner, the proposed CMS scheme shows 14% and 19% improvement in delay and power, respectively over CMS scheme proposed in [1].
Starting Page	389
Ending Page	392
Page Count	4
File Format	PDF
ISBN	9781605585222
DOI	10.1145/1531542.1531630
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-05-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Process variation tolerant Current mode singnaling Dynamic overdriving
Content Type	Text
Resource Type	Article

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