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An Efficient System On-Chip Interconnect using Modified Smart Bias Circuit-2014
| Content Provider | CiteSeerX |
|---|---|
| Author | Nithiya Devi., G. |
| Abstract | The most promising scheme for high-speed low power communication over long on-chip interconnects is Current-mode signaling (CMS) with dynamic overdriving scheme. A variation tolerant dynamic overdriving CMS scheme is proposed. The proposed CMS scheme employs a smart bias circuit in transmitter side. The smart bias is energy efficient and it reduces the delay. Current-mode signaling (CMS) scheme improves speed and reduces dynamic power consumption and it overcomes the drawback of voltage mode signaling. Although it consumes static power, it has a direct tradeoff between speed and static power. As the rise and fall delay is equal thereby it increases the throughput. However the voltage swing is decreased, the noise margin of data communication system get reduced. Dynamic over-driving is adopted for variation analysis which improves the energy, delay and EDP value over voltage mode signaling scheme. Keywords: |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Efficient System On-chip Interconnect Modified Smart Bias Circuit-2014 Cm Scheme Static Power Voltage Mode Long On-chip Interconnects Energy Efficient Variation Analysis Smart Bias Circuit Data Communication System Direct Tradeoff Equal Thereby Promising Scheme Transmitter Side Reduces Dynamic Power Consumption High-speed Low Power Communication Noise Margin Voltage Swing Current-mode Signaling Fall Delay Edp Value Smart Bias |
| Content Type | Text |
