NDLI: Spatial and temporal design debug using partial MaxSAT

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Spatial and temporal design debug using partial MaxSAT

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Spatial and temporal design debug using partial MaxSAT

Content Provider	ACM Digital Library
Author	Safarpour, Sean Veneris, Andreas Chen, Yibin Marques-Silva, Joao
Abstract	Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying possible error sources in the design. Unfortunately, these techniques do not provide any information regarding the time at which the bug is active during an error trace or counter-example. This work introduces an automated debug technique that provides the user with both spatial and temporal information about the source of error. The proposed method is based on a Partial MaxSAT formulation which models errors at the CNF clause level instead of the traditional gate or module level. Thus, error sites are identified based on erroneous implications that correspond to locations both in the design and in the error trace. Experiments demonstrate that we can provide this additional information at no extra cost in run time and are able to prune about 61% of all simulation time frames from the debugging process. When compared to a trivial formulation we observe a performance improvement of up to two orders of magnitude and 5× on average when using the proposed formulation.
Starting Page	345
Ending Page	350
Page Count	6
File Format	PDF
ISBN	9781605585222
DOI	10.1145/1531542.1531621
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-05-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Maximum satisfiability Design debugging
Content Type	Text
Resource Type	Article

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