NDLI: High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm

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High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm

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High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm

Content Provider	ACM Digital Library
Author	Sun, Yang Cavallaro, Joseph R.
Abstract	Maximum-likelihood (ML) decoding is a very computational-intensive task for multiple-input multiple-output (MIMO) wireless channel detection. This paper presents a new graph based algorithm to achieve near ML performance for soft MIMO detection. Instead of using the traditional tree search based structure, we represent the search space of the MIMO signals with a directed graph and a greedy algorithm is applied to compute the a posteriori probability (APP) for each transmitted bit. The proposed detector has two advantages: 1) it keeps a fixed throughput and has a regular and parallel datapath structure which makes it amenable to high speed VLSI implementation, and 2) it attempts to maximize the a posteriori probability by making the locally optimum choice at each stage with the hope of finding the global minimum Euclidean distance for every transmitted bit. Compared to the soft K-best detector, the proposed solution significantly reduces the complexity because sorting is not required, while still maintaining good bit error rate (BER) performance. The proposed greedy detection algorithm has been designed and synthesized for a 4 by 4 16-QAM MIMO system in a TSMC 65 nm CMOS technology. The detector achieves a maximum throughput of 600 Mbps with a 0.79 square mm core area.
Starting Page	445
Ending Page	450
Page Count	6
File Format	PDF
ISBN	9781605585222
DOI	10.1145/1531542.1531645
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-05-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Asic design Mimo detection Vlsi architecture
Content Type	Text
Resource Type	Article

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