NDLI: High-performance, cost-effective heterogeneous 3D FPGA architectures ( GLSVLSI '09 )

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High-performance, cost-effective heterogeneous 3D FPGA architectures

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High-performance, cost-effective heterogeneous 3D FPGA architectures ( GLSVLSI '09 )

Content Provider	ACM Digital Library
Author	Le, Roto Reda, Sherief Bahar, R. Iris
Abstract	In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized. Minimizing the total die area leads to direct manufacturing cost savings which is an important incentive to bring 3D technology to the fab and onto the market. An estimation framework is developed to assess the impact of silicon area utilized by 3D interconnect resources while taking into account the large area occupied by TSVs which is crucial to total die area of 3D FPGAs. In order to improve area and performance of 3D FPGAs, we design a novel 3D switch box with bypass TSVs. We also analyze the impact of different partitioning strategies on die area and find the optimal number of die that gives the largest reductions in total die area while maximizing the performance. Using a well-developed simulation infrastructure, we show that our methodologies can achieve an average reduction of 27.7% in total die area with a reduced interconnect path delay of about 58%.
Starting Page	251
Ending Page	256
Page Count	6
File Format	PDF
ISBN	9781605585222
DOI	10.1145/1531542.1531603
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-05-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	3d integrated circuits Heterogeneous fpga design
Content Type	Text
Resource Type	Article

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