NDLI: STI stress aware placement optimization based on geometric programming

Please wait, while we are loading the content...

Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems

Dynamic context management for low power coarse-grained reconfigurable architecture

Polynomial coefficient based DC testing of non-linear analog circuits

Soft error rate computation in early design stages using boolean satisfiability

Improved performance and yield with chip master planning design methodology

Glitch-free design for multi-threshold CMOS NCL circuits

Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems

Power efficient tree-based crosslinks for skew reduction

A reconfigurable stochastic architecture for highly reliable computing

Spatial and temporal design debug using partial MaxSAT

Buffer design and optimization for lut-based structured ASIC design styles

High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm

Dynamic reconfiguration approach for high speed turbo decoding using circular rings

DX-compactor: distributed X-compaction for SoCs

Intracortical wireless microsystems for biosensing and neurostimulation

Green computing: reducing energy cost and carbon footprint of information processing systems

Contact merging algorithm for efficient substrate noise analysis in large scale circuits

VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power

MYGEN: automata-based on-line test generator for assertion-based verification

Definition and application of approximate necessary assignments

Octilinear redistributive routing in bump arrays

Online circuit reliability monitoring

High-performance, cost-effective heterogeneous 3D FPGA architectures

Dual-threshold pass-transistor logic design

Bitmask-based control word compression for NISC architectures

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

A ubiquitous processor embedded with progressive cipher pipelines

High-throughput low-complexity MIMO detector based on K-best algorithm

A switchable PLL frequency synthesizer and hot carrier effects

Reliability aware NoC router architecture using input channel buffer sharing

Terahertz sensing technology

Design tools for emerging technologies

Simultaneous shield and repeater insertion

An interconnect-aware delay model for dynamic voltage scaling in NM technologies

An on-chip solution for static ADC test and measurement

Reducing parity generation latency through input value aware circuits

A stochastic-based efficient critical area extractor on OpenAccess platform

Process variation mitigation via post silicon clock tuning

On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design

A low-power CMOS thyristor based delay element with programmability extensions

Better than optimum?: register reduction using idle pipelined functional units

Robust window-based multi-node technology-independent logic minimization

Impact of lithography-friendly circuit layout

Hardware-accelerated gradient noise for graphics

On process variation tolerant low cost thermal sensor design in 32nm CMOS technology

A power-effective scan architecture using scan flip-flops clustering and post-generation filling

Circuits with light at the nanoscale: meta-nanocircuits and metactronics

Design challenges in high performance three-dimensional circuits

Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse

Voltage-island driven floorplanning considering level-shifter positions

Multi-level fault modeling for transaction-level specifications

Multicast routing with dynamic packet fragmentation

A taylor series methodology for analyzing the effects of process variation on circuit operation

The effect of design parameters on single-event upset sensitivity of MOS current mode logic

Power distribution paths in 3-D ICS

Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO

NBTI-aware sleep transistor design for reliable power-gating

Timing-driven N-way decomposition

A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

New performance/power/area efficient, reliable full adder design

State persistence: a property for guiding test generation

Disruptive technologies and neurally-inspired architectures

Safe clocking for the setup and hold timing constraints in datapath synthesis

Design of novel CAM core cell structures for an efficient implementation of low power BCAM system

Partitioned n-detection test generation

Energy efficient architecture of sensor network node based on compression accelerator

STI stress aware placement optimization based on geometric programming

Varicap threshold logic

A nine-context programmable optically reconfigurable gate array with semiconductor lasers

Complementary nano-electromechanical switches for ultra-low power embedded processors

Accelerating multi-party scheduling for transaction-level modeling

Deflecting crosstalk by routing reconsideration through refined signal correlation estimation

Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system

Router with centralized buffer for network-on-chip

Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding

A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits

Computing with field-coupled nanomagnets

Reducing temperature variability by routing heat pipes

Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation

Analysis of challenges for on-chip optical interconnects

Enhancing SAT-based sequential depth computation by pruning search space

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

RDL pre-assignment routing for flip-chip designs

On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers

A novel mechanism to dynamically switch speed and accuracy in systemC based transaction level models

Hierarchical state machine architecture for regular expression pattern matching

Redundant wire insertion for yield improvement

Central vs. distributed dynamic thermal management for multi-core processors: which one is better?

Incremental buffer insertion and module resizing algorithm using geometric programming

Energy-optimal synchronization primitives for single-chip multi-processors

Enhancing bug hunting using high-level symbolic simulation

Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors

Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices

A methodology for application-specific NoC architecture generation in a dynamic task structure environment

Physical unclonable function and true random number generator: a compact and scalable implementation

BISM: built-in self map for hybrid crossbar nano-architectures

Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels

The effects of logic partitioning in a majority logic based CMOS-NANO FPGA

A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic

A process variation tolerant self-compensating FinFET based sense amplifier design

A picosecond TDC architecture for multiphase PLLs

Study of leakage current mechanisms in ballistic deflection transistors

Low power and high performance sram design using bank-based selective forward body bias

Using soft-edge flip-flops to compensate NBTI-induced delay degradation

Contradictory antecedent debugging in bounded model checking

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature

A dual-MOSFET equivalent resistor thermal sensor

STI stress aware placement optimization based on geometric programming

Content Provider	ACM Digital Library
Author	Nakatake, Shigetoshi Dong, Qing Yang, Bo Li, Jing Hu, Xiaochuan
Abstract	Shallow trench isolation(STI) is the mainstream CMOS isolation technology for advanced integrated circuits. While STI process gives the isolation benefits due to its scalable characteristics, exploiting the compressive stress exerted by STI wells on device active regions to improve performance of devices has been one of the major industry focuses. However, in the present research of VLSI physical design, there has no yet a global optimization methodology on the whole chip layout to control the size of the STI wells, which affects the stress magnitude along with the size of active region of transistors. In this paper, we present a novel methodology that is capable of determining globally the optimal STI well width following the chip placement stage. The methodology is based on the observation that both of the terms in charge of chip width minimization and transistor channel mobility optimization in the objective function can be modeled as posynomials of the design variables, that is, the width of STI wells. Then, this stress aware placement optimization problem could be solved efficiently as a convex geometric programming (GP) problem. Finally, by a MOSEK GP problem solver, we do our STI width aware placement optimization on the given placements of some GSRC and IBM-PLACE benchmarks. Experiment results demonstrated that our methodology can obtain decent results with an acceptable runtime when satisfy the necessary location constraints from DRC specifications.
Starting Page	209
Ending Page	214
Page Count	6
File Format	PDF
ISBN	9781605585222
DOI	10.1145/1531542.1531594
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-05-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Sti stress Sti well width Placement optimization
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in