NDLI: Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

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Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

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Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

Content Provider	ACM Digital Library
Author	Ikenaga, Takeshi Goto, Satoshi Huang, Yiqing Liu, Qin
Abstract	In H.264/AVC based integer motion estimation engine, fixed architectures based on full pixel or direct sub-sampling pattern are widely used for HDTV application. However, these architectures suffer from either high complexity or quality loss problems. In this paper, an adaptive sub-sampling based reconfigurable architecture is given out. Firstly, by executing pixel difference analysis, the adaptive sub-sampling scheme which uses three hardware friendly patterns is applied on homogeneous macroblock (MB). Secondly, the related architecture introduces one more pipeline stage to build up configurable partial SAD values so that system performance is enhanced. Thirdly, a two-level pixel data organization scheme is proposed to solve data reuse and hardware utilization problems caused by adaptive algorithm. Moreover, one cross based SAD generation structure is introduced to achieve adaptive output results with less hardware cost. Experimental results show that, the proposed architecture can averagely save 61.71% clock cycles and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency is 208MHz under the TSMC 0.18um technology in worst case conditions(1.62V, 125 C).
Starting Page	463
Ending Page	468
Page Count	6
File Format	PDF
ISBN	9781605585222
DOI	10.1145/1531542.1531648
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-05-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Vlsi H.264 Reconfigurable architecture
Content Type	Text
Resource Type	Article

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