NDLI: Design space exploration and optimization of path oblivious RAM in secure processors

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Volume 41, Issue 5, December 2013

Volume 41, Issue 5, December 2013

Volume 41, Issue 4, September 2013

Volume 41, Issue 3, June 2013

Continuous real-world inputs can open up alternative accelerator designs

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Agile, efficient virtualization power management with low-latency server power states

Microarchitectural mechanisms to exploit value structure in SIMT architectures

Quantum rotations

Exploring memory consistency for massively-threaded throughput-oriented processors

Efficient virtual memory for big memory servers

Cooperative boosting

Orchestrated scheduling and prefetching for GPGPUs

Reducing memory access latency with asymmetric DRAM bank organizations

Bit mapping for balanced PCM cell programming

The locality-aware adaptive cache coherence protocol

On the feasibility of online malware detection with performance counters

Virtualizing power distribution in datacenters

Deconfigurable microprocessor architectures for silicon debug acceleration

An experimental study of data retention behavior in modern DRAM devices

Secure I/O device sharing among virtual machines on multiple hosts

Triggered instructions

DNA-based molecular architecture with spatially localized components

Navigating big data with high-throughput, energy-efficient data partitioning

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM

Tri-level-cell phase change memory

A new perspective for efficient virtual-cache coherence

Design space exploration and optimization of path oblivious RAM in secure processors

Convolution engine

Improving virtualization in the presence of software managed translation lookaside buffers

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Robust architectural support for transactional memory in the power architecture

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

Die-stacked DRAM caches for servers

Zombie memory: Extending memory lifetime by reviving dead blocks

Studying multicore processor scaling via reuse distance analysis

Non-race concurrency bug detection through order-sensitive critical sections

Thin servers with smart pipes

Improving memory scheduling via processor-side load criticality information

SIMD divergence optimization through intra-warp compaction

Resilient die-stacked DRAM caches

Criticality stacks

Volume 41, Issue 2, May 2013

Volume 41, Issue 1, March 2013

Design space exploration and optimization of path oblivious RAM in secure processors

Content Provider	ACM Digital Library
Author	van Dijk, Marten Devadas, Srinivas Fletcher, Christopher W. Ren, Ling Yu, Xiangyao
Abstract	Keeping user data private is a huge problem both in cloud computing and computation outsourcing. One paradigm to achieve data privacy is to use tamper-resistant processors, inside which users' private data is decrypted and computed upon. These processors need to interact with untrusted external memory. Even if we encrypt all data that leaves the trusted processor, however, the address sequence that goes off-chip may still leak information. To prevent this address leakage, the security community has proposed ORAM (Oblivious RAM). ORAM has mainly been explored in server/file settings which assume a vastly different computation model than secure processors. Not surprisingly, naïvely applying ORAM to a secure processor setting incurs large performance overheads. In this paper, a recent proposal called Path ORAM is studied. We demonstrate techniques to make Path ORAM practical in a secure processor setting. We introduce background eviction schemes to prevent Path ORAM failure and allow for a performance-driven design space exploration. We propose a concept called super blocks to further improve Path ORAM's performance, and also show an efficient integrity verification scheme for Path ORAM. With our optimizations, Path ORAM overhead drops by 41.8%, and SPEC benchmark execution time improves by 52.4% in relation to a baseline configuration. Our work can be used to improve the security level of previous secure processors.
Starting Page	571
Ending Page	582
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2508148.2485971
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	41
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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