NDLI: Non-race concurrency bug detection through order-sensitive critical sections

Please wait, while we are loading the content...

Volume 41, Issue 5, December 2013

Volume 41, Issue 5, December 2013

Volume 41, Issue 4, September 2013

Volume 41, Issue 3, June 2013

Continuous real-world inputs can open up alternative accelerator designs

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Agile, efficient virtualization power management with low-latency server power states

Microarchitectural mechanisms to exploit value structure in SIMT architectures

Quantum rotations

Exploring memory consistency for massively-threaded throughput-oriented processors

Efficient virtual memory for big memory servers

Cooperative boosting

Orchestrated scheduling and prefetching for GPGPUs

Reducing memory access latency with asymmetric DRAM bank organizations

Bit mapping for balanced PCM cell programming

The locality-aware adaptive cache coherence protocol

On the feasibility of online malware detection with performance counters

Virtualizing power distribution in datacenters

Deconfigurable microprocessor architectures for silicon debug acceleration

An experimental study of data retention behavior in modern DRAM devices

Secure I/O device sharing among virtual machines on multiple hosts

Triggered instructions

DNA-based molecular architecture with spatially localized components

Navigating big data with high-throughput, energy-efficient data partitioning

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM

Tri-level-cell phase change memory

A new perspective for efficient virtual-cache coherence

Design space exploration and optimization of path oblivious RAM in secure processors

Convolution engine

Improving virtualization in the presence of software managed translation lookaside buffers

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Robust architectural support for transactional memory in the power architecture

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

Die-stacked DRAM caches for servers

Zombie memory: Extending memory lifetime by reviving dead blocks

Studying multicore processor scaling via reuse distance analysis

Non-race concurrency bug detection through order-sensitive critical sections

Thin servers with smart pipes

Improving memory scheduling via processor-side load criticality information

SIMD divergence optimization through intra-warp compaction

Resilient die-stacked DRAM caches

Criticality stacks

Volume 41, Issue 2, May 2013

Volume 41, Issue 1, March 2013

Non-race concurrency bug detection through order-sensitive critical sections

Content Provider	ACM Digital Library
Author	Suh, G. Edward Halberg, Erik Huang, Ruirui
Abstract	This paper introduces a new heuristic condition for non-race concurrency bugs, named order-sensitive critical sections, and proposes a run-time bug detection scheme based on the condition. The order-sensitive critical sections are defined as a pair of critical sections that can lead to non-deterministic shared memory state depending on the order in which they execute. In a sense, the order-sensitive critical sections can be seen as extending the intuition in using data races as a potential bug condition to capture non-race bugs. Experiments show that the proposed scheme provides a good coverage for multiple types of non-race bugs, with a small number of false positives. For example, the scheme detected all 9 real-world non-race bugs that were tested as well as over 90% of injected non-race bugs. Additionally, this paper presents an efficient hardware architecture that supports the proposed scheme with minor hardware changes and a small amount of additional state - a 9-KB buffer per core and a 1-bit tag per data cache block. The hardware-based scheme could still detect all 9 real-world bugs that were tested and more than 84% of the injected non-race bugs. Moreover, the hardware supported scheme has a negligible impact on performance, with a 0.23% slowdown on average.
Starting Page	655
Ending Page	666
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2508148.2485978
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	41
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in