NDLI: Continuous real-world inputs can open up alternative accelerator designs

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Volume 41, Issue 5, December 2013

Volume 41, Issue 5, December 2013

Volume 41, Issue 4, September 2013

Volume 41, Issue 3, June 2013

Continuous real-world inputs can open up alternative accelerator designs

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Agile, efficient virtualization power management with low-latency server power states

Microarchitectural mechanisms to exploit value structure in SIMT architectures

Quantum rotations

Exploring memory consistency for massively-threaded throughput-oriented processors

Efficient virtual memory for big memory servers

Cooperative boosting

Orchestrated scheduling and prefetching for GPGPUs

Reducing memory access latency with asymmetric DRAM bank organizations

Bit mapping for balanced PCM cell programming

The locality-aware adaptive cache coherence protocol

On the feasibility of online malware detection with performance counters

Virtualizing power distribution in datacenters

Deconfigurable microprocessor architectures for silicon debug acceleration

An experimental study of data retention behavior in modern DRAM devices

Secure I/O device sharing among virtual machines on multiple hosts

Triggered instructions

DNA-based molecular architecture with spatially localized components

Navigating big data with high-throughput, energy-efficient data partitioning

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM

Tri-level-cell phase change memory

A new perspective for efficient virtual-cache coherence

Design space exploration and optimization of path oblivious RAM in secure processors

Convolution engine

Improving virtualization in the presence of software managed translation lookaside buffers

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Robust architectural support for transactional memory in the power architecture

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

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Studying multicore processor scaling via reuse distance analysis

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Thin servers with smart pipes

Improving memory scheduling via processor-side load criticality information

SIMD divergence optimization through intra-warp compaction

Resilient die-stacked DRAM caches

Criticality stacks

Volume 41, Issue 2, May 2013

Volume 41, Issue 1, March 2013

Continuous real-world inputs can open up alternative accelerator designs

Content Provider	ACM Digital Library
Author	Li, Zheng Joubert, Antoine Belhadj, Bilel Héliot, Rodolphe Temam, Olivier
Abstract	Motivated by energy constraints, future heterogeneous multi-cores may contain a variety of accelerators, each targeting a subset of the application spectrum. Beyond energy, the growing number of faults steers accelerator research towards fault-tolerant accelerators. In this article, we investigate a fault-tolerant and energy-efficient accelerator for signal processing applications. We depart from traditional designs by introducing an accelerator which relies on unary coding, a concept which is well adapted to the continuous real-world inputs of signal processing applications. Unary coding enables a number of atypical micro-architecture choices which bring down area cost and energy; moreover, unary coding provides graceful output degradation as the amount of transient faults increases. We introduce a configurable hybrid digital/analog micro-architecture capable of implementing a broad set of signal processing applications based on these concepts, together with a back-end optimizer which takes advantage of the special nature of these applications. For a set of five signal applications, we explore the different design tradeoffs and obtain an accelerator with an area cost of $1.63mm^{2}.$ On average, this accelerator requires only 2.3% of the energy of an Atom-like core to implement similar tasks. We then evaluate the accelerator resilience to transient faults, and its ability to trade accuracy for energy savings.
Starting Page	1
Ending Page	12
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2508148.2485923
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	41
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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