NDLI: A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

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Volume 41, Issue 5, December 2013

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Continuous real-world inputs can open up alternative accelerator designs

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Agile, efficient virtualization power management with low-latency server power states

Microarchitectural mechanisms to exploit value structure in SIMT architectures

Quantum rotations

Exploring memory consistency for massively-threaded throughput-oriented processors

Efficient virtual memory for big memory servers

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Orchestrated scheduling and prefetching for GPGPUs

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Bit mapping for balanced PCM cell programming

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On the feasibility of online malware detection with performance counters

Virtualizing power distribution in datacenters

Deconfigurable microprocessor architectures for silicon debug acceleration

An experimental study of data retention behavior in modern DRAM devices

Secure I/O device sharing among virtual machines on multiple hosts

Triggered instructions

DNA-based molecular architecture with spatially localized components

Navigating big data with high-throughput, energy-efficient data partitioning

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM

Tri-level-cell phase change memory

A new perspective for efficient virtual-cache coherence

Design space exploration and optimization of path oblivious RAM in secure processors

Convolution engine

Improving virtualization in the presence of software managed translation lookaside buffers

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Robust architectural support for transactional memory in the power architecture

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

Die-stacked DRAM caches for servers

Zombie memory: Extending memory lifetime by reviving dead blocks

Studying multicore processor scaling via reuse distance analysis

Non-race concurrency bug detection through order-sensitive critical sections

Thin servers with smart pipes

Improving memory scheduling via processor-side load criticality information

SIMD divergence optimization through intra-warp compaction

Resilient die-stacked DRAM caches

Criticality stacks

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Volume 41, Issue 1, March 2013

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Content Provider	ACM Digital Library
Author	Asanovic, Krste Dao, Khanh Cook, Henry Bird, Sarah Patterson, David A. Moreto, Miquel
Abstract	Computing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on disjoint sets of resources, but this incurs additional energy, power, and capital costs. In this paper, we evaluate the potential of hardware cache partitioning mechanisms and policies to improve efficiency by allowing background applications to run simultaneously with interactive foreground applications, while avoiding degradation in interactive responsiveness. We evaluate these tradeoffs using commercial x86 multicore hardware that supports cache partitioning, and find that real hardware measurements with full applications provide different observations than past simulation-based evaluations. Co-scheduling applications without LLC partitioning leads to a 10% energy improvement and average throughput improvement of 54% compared to running tasks separately, but can result in foreground performance degradation of up to 34% with an average of 6%. With optimal static LLC partitioning, the average energy improvement increases to 12% and the average throughput improvement to 60%, while the worst case slowdown is reduced noticeably to 7% with an average slowdown of only 2%. We also evaluate a practical low-overhead dynamic algorithm to control partition sizes, and are able to realize the potential performance guarantees of the optimal static approach, while increasing background throughput by an additional 19%.
Starting Page	308
Ending Page	319
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2508148.2485949
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	41
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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