NDLI: FabScalar:composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

Content Provider	ACM Digital Library
Author	Wadhavkar, Salil V. Mayukh, Hiran Najaf-abadi, Hashem H. Choudhary, Niket K. Navada, Sandeep Gandhi, Jayneel Dwiel, Brandon H. Rotenberg, Eric Shah, Tanmay A.
Abstract	A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-designed superscalar core types that can streamline the execution of diverse programs and program phases. No prior research has addressed the 'Achilles' heel of this paradigm: design and verification effort is multiplied by the number of different core types. This work frames superscalar processors in a canonical form, so that it becomes feasible to quickly design many cores that differ in the three major superscalar dimensions: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP). From this idea, we develop a toolset, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template. The template defines canonical pipeline stages and interfaces among them. A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage, that differ in their superscalar width and depth of sub-pipelining. An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Validation experiments are performed along three fronts to evaluate the quality of RTL designs generated by FabScalar: functional and performance (instructions-per-cycle (IPC)) validation, timing validation (cycle time), and confirmation of suitability for standard ASIC flows. With FabScalar, a chip with many different superscalar core types is conceivable.
Starting Page	11
Ending Page	22
Page Count	12
File Format	PDF MP4
ISSN	01635964
DOI	10.1145/2024723.2000067
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	39
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Custom processors Superscalar processors Heterogeneous (asymmetric) multi-core Instruction-level parallelism (ilp)
Content Type	Audio Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template (2011)

FabScalar: Automating Superscalar Core Design

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Bahurupi: A polymorphic heterogeneous multi-core architecture

Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters

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FabScalar:composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

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FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

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FabScalar:composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template