NDLI: Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters

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ACM Transactions on Architecture and Code Optimization (TACO) : Volume 13

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The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence

DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era

Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters

Leveraging Transactional Execution for Memory Consistency Model Emulation

CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion

Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency

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Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters

Content Provider	ACM Digital Library
Author	Seznec, André Mondelli, Andrea Michaud, Pierre
Copyright Year	2015
Abstract	During the past 10 years, the clock frequency of high-end superscalar processors has not increased. Performance keeps growing mainly by integrating more cores on the same chip and by introducing new instruction set extensions. However, this benefits only some applications and requires rewriting and/or recompiling these applications. A more general way to accelerate applications is to increase the IPC, the number of instructions executed per cycle. Although the focus of academic microarchitecture research moved away from IPC techniques, the IPC of commercial processors was continuously improved during these years. We argue that some of the benefits of technology scaling should be used to raise the IPC of future superscalar cores further. Starting from microarchitecture parameters similar to recent commercial high-end cores, we show that an effective way to increase the IPC is to allow the out-of-order engine to issue more micro-ops per cycle. But this must be done without impacting the clock cycle. We propose combining two techniques: clustering and register write specialization. Past research on clustered microarchitectures focused on narrow issue clusters, as the emphasis at that time was on allowing high clock frequencies. Instead, in this study, we consider wide issue clusters, with the goal of increasing the IPC under a constant clock frequency. We show that on a wide issue dual cluster, a very simple steering policy that sends 64 consecutive instructions to the same cluster, the next 64 instructions to the other cluster, and so forth, permits tolerating an intercluster delay of three cycles. We also propose a method for decreasing the energy cost of sending results from one cluster to the other cluster.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/2800787
Volume Number	12
Issue Number	3
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-08-31
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Clustered microarchitecture Instruction-level parallelism Steering policy Superscalar core
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FabScalar: Automating Superscalar Core Design

Bahurupi: A polymorphic heterogeneous multi-core architecture

Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism

Abstract Microarchitecture for Billion-Transistor VLSI Superscalar Processors (2002)

Revisiting Wide Superscalar Microarchitecture

Tuning the continual flow pipeline architecture with virtual register renaming

Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores

Software thread integration for instruction-level parallelism

Toward kilo-instruction processors

Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters

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