NDLI: Fully integrated fractional-N phase-locked loop for GNSS standards

Content Provider	IET Digital Library
Author	Kashani, Zahra Ghattan Avanji, Seyed Amin Izadi
Abstract	This study presents the design of a fully integrated fractional-N phase-locked loop (FNPLL) for the Global Navigation Satellite System (GNSS) applications. A new linearisation technique is presented for a charge pump (CP) circuit to improve the mismatch between the charging and discharging currents. The linearised currents help to reduce the static phase offset and the reference spurs of the FNPLL and the constant current helps to control the PLL dynamics precisely. The presented FNPLL is designed in a 0.18 µm CMOS technology. The simulation result reveals that the linearity of the CP is enhanced greatly when the technique is enabled and the current mismatch is <0.2 µA over the output voltage ranging from 0.2 to 1.65 V. The phase noise of the FNPLL at 10 and 100 KHz offset frequencies without the linearised CP are −85 and −90 dBc/Hz, respectively, and with the high linear CP are −90 and −97 dBc/Hz, respectively. The output power spectral density of the FNPLL shows that the power of the highest fractional spur is about −57 dBc. The lock time and the power consumption of the designed FNPLL are 50 µs and 11 mW from a 1.8 V power supply, respectively.
Starting Page	2391
Ending Page	2395
Page Count	5
ISSN	17518725
Volume Number	13
e-ISSN	17518733
Issue Number	Issue 13, Oct (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-map/13/13
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.5528
Journal	IET Microwaves, Antennas & Propagation
Publisher Date	2019-07-08
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Analogue Circuit Charge Pump Circuit CMOS Integrated Circuit CMOS Technology Constant Current Current Mismatch Demodulator Discriminators And Mixers FNPLL Fractional Spur Fully Integrated Fractional-N Phase-locked Loop Global Navigation Satellite System GNSS Standards Integrated Circuit Design Layout Linearisation Technique Linearised Current Modelling And Testing Modulator Output Power Spectral Density Phase Locked Loop Phase Noise PLL Dynamics Power 11.0 MW Power Consumption Radio Navigation And Direction Finding Reference Spurs Satellite Navigation Semiconductor Integrated Circuit Design Size 0.18 Mum Static Phase Offset Time 50.0 Mus Voltage 0.2 V to 1.65 V Voltage 1.8 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Current pulse shaping technique for low spur fractional-N phase-locked loop

Phase-error cancellation technique for fast-lock phase-locked loop

High swing PLL charge pump with current mismatch reduction

Low-power charge-steering phase interpolator

Simple high-resolution CMOS phase frequency detector

Spur reduction architecture for multiphase fractional PLLs

2 GHz sub-harmonically injection-locked PLL with mixer-based injection timing control in 0.18 µm CMOS technology

Phase-interpolator-based glitch-free fractional frequency divider with track-and-hold technique

Fractional spur reduction technique using 45° phase dithering in phase interpolator based all-digital phase-locked loop

Fully integrated fractional-N phase-locked loop for GNSS standards

Similar Documents

Current pulse shaping technique for low spur fractional-N phase-locked loop

Phase-error cancellation technique for fast-lock phase-locked loop

High swing PLL charge pump with current mismatch reduction

Low-power charge-steering phase interpolator

Simple high-resolution CMOS phase frequency detector

Spur reduction architecture for multiphase fractional PLLs

2 GHz sub-harmonically injection-locked PLL with mixer-based injection timing control in 0.18 µm CMOS technology

Phase-interpolator-based glitch-free fractional frequency divider with track-and-hold technique

Fractional spur reduction technique using 45° phase dithering in phase interpolator based all-digital phase-locked loop

Fully integrated fractional-N phase-locked loop for GNSS standards