NDLI: Low-power and high-speed 13T SRAM cell using FinFETs

Content Provider	IET Digital Library
Author	Saxena, Shilpa Mehra, Rajesh
Abstract	Fin field-effect transistors (FinFETs) are replacing the traditional planar metal–oxide–semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.
Starting Page	250
Ending Page	255
Page Count	6
ISSN	1751858X
Volume Number	11
e-ISSN	17518598
Issue Number	Issue 3, May (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/11/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2016.0287
Journal	IET Circuits, Devices & Systems
Publisher Date	2016-11-24
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Access Path Device-performance Variability Mitigation Digital Circuit Design, Modelling And Testing Dopant Ions Enhancement Method Fin Field-effect Transistors FinFET Transistor Structure Gate Controllability Gate Scalability High-speed 13T SRAM Cell Insulated Gate Field Effect Transistors Integrated Circuit Design Intrinsic Body Leakage Current Low Power Electronics Low-power Static-random Access Memory Cell Memory Circuit MOSFET Parameter Fluctuations Performance Analysis Planar Complementary MOS Technology Power Dissipation Power Gating Technique Power Reduction Propagation Delay Semiconductor Storage Short Channel Effect Sleep Transistors Approach Speed Improvement SRAM Chips ST11T Cell Transmission Gate
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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