NDLI: Scalable GF(p) Montgomery multiplier based on a digit

Content Provider	IET Digital Library
Author	Sandoval, M. Morales Perez, A. Diaz
Abstract	This study presents a scalable hardware architecture for modular multiplication in prime fields GF(p). A novel iterative digit–digit Montgomery multiplication (IDDMM) algorithm is proposed and two hardware architectures that compute that algorithm are described. The input operands (multiplicand, multiplier and modulus) are represented using as radix β = 2 k . Multiplication over GF(p) is possible using almost the same hardware since the complexity of multiplier's kernel module depends mainly on k and not on p. The novel hardware architectures of GF(p) multipliers were evaluated on three Xilinx FPGA families. Design trade-offs were analysed considering different operand sizes commonly used in cryptography and different digits sizes. The proposed designs for IDDMM are well suited to be implemented in modern FPGAs, making use of available dedicated multipliers and memory blocks reducing drastically the FPGA's standard logic while keeping an acceptable performance compared with other implementation approaches. From the Virtex5 implementation, the proposed MM multiplier reaches a throughput of 242 Mbps using only 219 FPGA slices and achieving a 1024-bit modular multiplication in 4.21μs. This is 26 times less area resources than similar related works in the literature with an improved efficiency of 7x.
Starting Page	102
Ending Page	109
Page Count	8
ISSN	17518601
Volume Number	10
e-ISSN	1751861X
Issue Number	Issue 3, May (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/10/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2015.0055
Journal	IET Computers & Digital Techniques
Publisher Date	2016-05-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Bit Rate 242 Mbit/s Code Cryptography Design Trade-off Analysis Digit Sizes Digit-digit Computation Approach Field Programmable Gate Array Galois Field IDDMM Algorithm Iterative Digit–digit Montgomery Multiplication Algorithm Logic And Switching Circuit Logic Circuit Memory Blocks Multiplier Kernel Module Complexity Multiplying Circuit Scalable GF(p) Montgomery Multiplier Scalable Hardware Architecture Time 4.21 Mus Virtex5 Word Length 1024 Bit Xilinx FPGA Family
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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