NDLI: Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network

Content Provider	IET Digital Library
Author	Murty, Mahesh S. Shrestha, Rahul
Abstract	This paper presents reconfigurable and hardware-efficient VLSI architecture of time domain cyclostationary-feature detector (TCD) for spectrum sensing in the cognitive-radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE-Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware-efficient techniques have been introduced for the multiply-&-accumulate and accumulator architectures of suggested TCD design. Real-world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post-layout simulation of the proposed detector have been performed using 65 nm-CMOS technology and it occupies 0.32 mm2 of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state-of-the-art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively
Starting Page	542
Ending Page	550
Page Count	9
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 5, Sep (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0292
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-02-20
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	4G LTE-Advanced 4G Mobile Communication Accumulator Architectures Additive White Gaussian Noise Channel Environment Application Specific Integrated Circuit Application Specific Integrated Circuit Synthesis Autocorrelator AWGN Channel Clock Frequency CMOS Integrated Circuit Cognitive Radio Field Programmable Gate Array FPGA Frequency 1.0 MHz Frequency 100.0 MHz Hardware-efficient Technique Hardware-efficient Very Large-scale Integration Architecture Integrated Circuit Layout Layout Logic Circuit Long Term Evolution Mobile Radio System Modelling And Testing Modulation And Coding Method Multiply-&-accumulate Architecture Next Generation Network Next-generation LTE-A Cognitive-radio Wireless Network OFDM Modulation OFDM Signal OFDM-based Communication System Orthogonal Frequency Division Multiplexing System Overflow-underflow Protection Performance Analysis Post-layout Simulation Power 18.5 MW Radio Spectrum Management Real-world Signal Rotation Digital Computer Engine Semiconductor Integrated Circuit Design Signal Detection Signal to Noise Ratio Size 65 Nm Software Radio Spectrum Sensing Spectrum Sensor TCD Design Time 5.12 Ms Time-domain Cyclostationary-feature Detector United-microelectronics-corporation Complementary Metal–oxide–semiconductor Technology Universal Software Radio Peripheral Device VLSI VLSI Design Wireless Sensor Network
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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