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Content Provider | IET Digital Library |
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Author | Deng, Xiaoying Mo, Yanyan |
Abstract | A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors. |
Starting Page | 680 |
Ending Page | 682 |
Page Count | 3 |
ISSN | 00135194 |
Volume Number | 51 |
e-ISSN | 1350911X |
Issue Number | Issue 9, Apr (2015) |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/51/9 |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2014.3845 |
Journal | Electronics Letters |
Publisher Date | 2015-04-16 |
Access Restriction | Open |
Rights Holder | © The Institution of Engineering and Technology |
Subject Keyword | Amplifiers BBDSAFF Boost Bulk-driven Sense-amplifier Flip-flop Counter-clock System Energy 2.73 FJ Energy 3.32 FJ Flip Flops Logic And Switching Circuit Logic Circuit Microprocessor PDP Power 29 MuW Power 31 MuW Power Dissipation PseudoPMOS Dynamic Technique RS Latch Output Stage Strollo Sense-amplifier-based Flip-flop Symmetrical Rise/fall Delay Time 107 Ps Time 94 Ps Ultradynamic Voltage Scaling VLSI Circuit |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering |
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