NDLI: LDPC check node implementation using reversible logic

Content Provider	IET Digital Library
Author	Awais, Muhammad Razzaq, Anas Ahmed, Ashfaq Masera, Guido
Abstract	Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm2, achieves up to 4.3 GHz frequency and consumes 52 μ W power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.
Starting Page	443
Ending Page	455
Page Count	13
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 4, Jul (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5222
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-05-30
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Check Node Processor CMOS Integrated Circuit CN Functionality Code Complementary Metal–oxide–semiconductor Technology Decoding Decoding Algorithm Digital Circuit Design, Modelling And Testing Digital Design Paradigm Forward Error Correction Forward Error Correction Domain Information-lossless Nature LDPC Check Node Implementation LDPC Decoding Logic And Switching Circuit Logic Circuit Logic Design Method Logic Element Logic Gate Low Density Parity Check Decoding Low Energy Dissipation Low Power Electronics Low-power LDPC CN Architecture Parity Check Code Postlayout Area Postlayout Simulations Power Delay Product Practical Complexity Application Reversible Blocks Reversible Logic Gate Schematic Checks Transistor Transistor Level Design
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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