NDLI: Clockless Stochastic Decoding of Low-Density Parity-Check Codes

Content Provider	IEEE Xplore Digital Library
Author	Onizawa, N. Gross, W.J. Hanyu, T. Gaudet, V.C.
Copyright Year	2012
Abstract	This paper introduces clock less stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clock less decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes, however, it does not significantly affect output probabilities. A timing model of clock less-computation behaviours under a 90nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the ``lock-up", problem and achieves superior BER performance compared with conventional synchronous stochastic decoders.
Starting Page	143
Ending Page	148
File Size	213652
Page Count	6
File Format	PDF
ISBN	9781467329866
ISSN	21623562
e-ISBN	9781467329873
DOI	10.1109/SiPS.2012.53
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-17
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Synchronization Parity check codes Stochastic processes Bit error rate Logic gates circuit implementation stochastic computation iterative decoding forward error correction codes clockless computation
Content Type	Text
Resource Type	Article

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