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Low-cost security aware HLS methodology

Content Provider	IET Digital Library
Author	Sengupta, Anirban Bhadauria, Saumya Mohanty, Saraju P.
Abstract	Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4%) through the proposed approach compared with a recent approach.
Starting Page	68
Ending Page	79
Page Count	12
ISSN	17518601
Volume Number	11
e-ISSN	1751861X
Issue Number	Issue 2, Mar (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/11/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2016.0014
Journal	IET Computers & Digital Techniques
Publisher Date	2016-09-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Candidate Datapath Resource Configuration Data Security Design Process Globalisation Design Space Digital Circuit Design, Modelling And Testing Digital Integrated Circuit Electronic Engineering Computing Encoding Hardware Threats High Level Synthesis Industrial Property Integrated Circuit Design Intellectual Property Cores Invasive Software IP Cores Low-cost Optimised Dual Modular Redundant Design Low-cost Security Aware HLS Methodology Low-cost Security-aware HLS Approach Low-cost Trojan Secured Schedule Resource Allocation Scheduling Third Party Vendors Trojan Secured High-level Synthesis Methodology User Constraint Vendor Allocation Information Vendor Allocation Procedure Exploration Process
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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