NDLI: Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits

Content Provider	IET Digital Library
Author	Ahmad, Imtiaz Imdoukh, Mahmoud Alfailakawi, Mohammad Gh.
Abstract	Shifting market trends towards mobile, Internet of things, and data-centric applications create opportunities for emerging low-power non-volatile memories. The attractive features of spin-torque-transfer magnetic-RAM (STT-MRAM) make it a promising candidate for future on-chip cache memory. Two-bit multiple-level cell (MLC) STT-MRAMs suffer from higher write energy, performance overhead, and lower cell endurance when compared with single-level counterpart. These unwanted effects are mainly due to write operations known as two-step (TT) and hard transitions (HT). Here, the authors offer a solution to tackle write energy problem in MLC STT-MRAM by minimising the number of TT and HT transitions. By analysing real applications, it was observed that specific locations within a cache block undergo much more TT and HT transitions resulting in hot locations when compared with other ones (cold locations). These hot locations are more detrimental to the lifetime and reliability of MRAM device. In this work, the authors propose a simple and intuitive dynamic encoding scheme that eliminates all TT and HT at hot locations, hence reducing energy consumption and improving MLC STT-MRAM lifetime. Results on PARSEC benchmarks demonstrate the effectiveness and scalability of the proposed approach to potentially prolong MLC STT-MRAM lifetime.
Starting Page	214
Ending Page	220
Page Count	7
ISSN	17518601
Volume Number	11
e-ISSN	1751861X
Issue Number	Issue 6, Nov (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/11/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2017.0089
Journal	IET Computers & Digital Techniques
Publisher Date	2017-08-17
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Hard Transitions Memory Circuit MLC STT-MRAM On-chip Cache Memory Random-access Storage Semiconductor Storage Spin-torque-transfer Magnetic-RAM Two-bit Multiple-level Cell STT-MRAM Two-step
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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