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Content Provider | IET Digital Library |
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Author | Wieczorek, P. Z. |
Abstract | True random number generators (TRNGs) based on flip-flop (FF) metastability can suffer from sensitivity to frequency injection attacks. A dedicated attack can interfere with a FF's initial condition and influence the logical state or resolve time. These, in turn might result in significant keyspace reduction. Therefore, a novel TRNG utilising random timing of metastable FF is proposed. In this concept, a programmable delay line driven by a pseudo-random generator with a random seed, changes continuously the phase between triggering signals (data and clock) and the global system clock. Nevertheless, the relative interval of clock and data active slopes remains constant and violates FF timing to ensure metastable (truly random) operation. |
Starting Page | 384 |
Ending Page | 386 |
Page Count | 3 |
ISSN | 00135194 |
Volume Number | 51 |
e-ISSN | 1350911X |
Issue Number | Issue 5, Mar (2015) |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/51/5 |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2014.4030 |
Journal | Electronics Letters |
Publisher Date | 2015-02-20 |
Access Restriction | Open |
Rights Holder | © The Institution of Engineering and Technology |
Subject Keyword | Digital Arithmetic Method Flip Flops Flip-flop Metastability Frequency Injection Attack GCK Global System Clock KeySpace Reduction Logic And Switching Circuit Logic Circuit Logical State Programmable Delay Line Pseudo-random Generator Random Number Generation Resolve Time Triggering Signal TRNG True Random Number Generator |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering |
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