NDLI: FPGA-based RO PUF with low overhead and high stability

Content Provider	IET Digital Library
Author	Zhou, Kai Liang, Huaguo Jiang, Yue Huang, Zhengfeng Jiang, Cuiyun Lu, Yingchun
Abstract	Ring oscillator physical unclonable functions (RO PUF) promise cheap, efficient, and secure identification and authentication of the chip. However, RO PUF typically has high hardware overhead, and it is difficult to guarantee its stability due to the complex operating environment. In this Letter, the programmable delay lines were utilised to configure the ring oscillator to improve the performance of PUF on FPGA. The proposed structure generates a 16-bit reliable PUF response using only two slices. Experimental results show that the proposed PUF has low hardware overhead, and multiple measurements under a wide range of operating environments demonstrate that it is highly stable.
Starting Page	510
Ending Page	513
Page Count	4
ISSN	00135194
Volume Number	55
e-ISSN	1350911X
Issue Number	Issue 9, May (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/55/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2019.0451
Journal	Electronics Letters
Publisher Date	2019-03-21
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Chip Identification Circuit Stability Complex Operating Environment Cryptography Field Programmable Gate Array FPGA-based RO PUF High Hardware Overhead Logic And Switching Circuit Logic Circuit Low Hardware Overhead Oscillator Programmable Delay Line Reliability Reliable PUF Response Ring Oscillator Ring Oscillator Physical Unclonable Function Secure Identification Word Length 16 Bit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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