NDLI: DHL-cache: dynamic per history length adjustment for low-power L2 cache

Content Provider	IET Digital Library
Author	Joo, H. W. Chung, E. Y.
Abstract	The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energy-delay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.
Starting Page	1297
Ending Page	1298
Page Count	2
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 15, Jul (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/15
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.1465
Journal	Electronics Letters
Publisher Date	2016-06-29
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Access History Pattern Associative Storage Cache Storage Content-addressable Storage DHL-cache Dynamic Per History Length Adjustment Cache Energy-delay Product Improvement Fragmented Locality High-associative Large-L2 Cache L1 Cache Low Power Electronics Low-power L2 Cache Memory Circuit Microprocessor Chips Microprocessors Microprocessors And Microcomputer Minimum Hardware Support On-chip L2 Cache Power Dissipation Way-prediction Accuracy Way-prediction Window Size
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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