NDLI: 5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

Content Provider	IET Digital Library
Author	Alsuraisry, H. Wu, M. H. Huang, P. S. Tsai, J. H. Huang, T. W.
Abstract	A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode configuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm2 in 0.263 mm2 chip area to date.
Starting Page	1338
Ending Page	1340
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 15, Jul (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/15
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.1629
Journal	Electronics Letters
Publisher Date	2016-06-30
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Cascode Configuration CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Process Compact Circuit Size Efficiency 42 Percent Field Effect MMIC Frequency 5.3 GHz Fully Integrated Class-E PA Design High Gain Property High-efficiency Class-E Power Amplifier Inductor Loss Low Drain-to-source Parasitic Capacitor Low-cost Class-E Power Amplifier Microwave IC MMIC Power Amplifiers Optimised RF Choke Inductor PAE Class-E Power Amplifier Power Area Density Size 180 Nm
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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