NDLI: SkipCache: application aware cache management for chip multi-processors

Content Provider	IET Digital Library
Author	Warrier, Tripti S. Raghavendra, Kanakagiri Mutyam, Madhu
Abstract	With the advent of multiple cores on a single chip, it is common for the systems to have multi-level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of study revolves around one question: are all levels of cache needed by all applications during all phases of their execution? The study observes the effect of 2-level and 3-level cache hierarchies on the performance of different applications. On the basis of this study, this study proposes an application aware cache management policy called ‘SkipCache’, which allows an application to choose a 2-level or 3-level cache hierarchy during run-time. SkipCache dynamically tracks the applications at shared last-level cache (LLC) to identify the applications that do not obtain advantage by using the LLC. Such applications can completely skip the LLC so that other co-scheduled cache friendly applications can efficiently use it. Evaluation of SkipCache in a 4-core chip multi-processor with multi-programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimisation techniques to improve the system performance.
Starting Page	293
Ending Page	299
Page Count	7
ISSN	17518601
Volume Number	9
e-ISSN	1751861X
Issue Number	Issue 6, Nov (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/9/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2014.0150
Journal	IET Computers & Digital Techniques
Publisher Date	2015-05-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	2-level Cache Hierarchy 3-level Cache Hierarchy 4-core Chip Multi-processor Application Aware Cache Management Cache Storage Chip Multi-processors Memory Bandwidth Memory Circuit Microprocessor Chips Microprocessors And Microcomputer Multiprocessing System Optimisation Optimisation Technique Semiconductor Storage Shared Last-level Cache SkipCache
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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