NDLI: 0.012 mm2 800 µW 0.1–6.4 GHz multi-protocol PLL with 14 psrms integrated jitter in 28 nm FD-SOI

Content Provider	IET Digital Library
Author	Gupta, N. Lahiri, A. Kumar, A.
Abstract	A multi-protocol PLL suitable for different wireline standards namely HDMI1.4, USB2.0, DDR4, DisplayPort1.2 and for host clock generation for low-power system-on-chips is presented. The PLL employs automatic VCO gain and charge-pump current calibration circuits to provide a near constant PLL bandwidth which enables a robust jitter performance across process, voltage, temperature. Without increasing the loop-filter capacitor, dual-path loop-filter technique is employed to reduce output jitter due to thermal noise of loop-filter resistor. The PLL designed in 28 nm fully depleted silicon on insulator (FD-SOI) process has an output frequency range from 0.1 to 6.4 GHz, total rms integrated jitter of 14 ps at 21.25 MHz reference frequency, consumes 800 µW at 3.4 GHz VCO frequency and occupies an area of 0.012 mm2.
Starting Page	1518
Ending Page	1520
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 18, Sep (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/18
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.0819
Journal	Electronics Letters
Publisher Date	2016-08-12
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Automatic VCO Gain Charge Pump Circuit Charge-pump Current Calibration Circuit DDR4 Demodulator Discriminators And Mixers DisplayPort1.2 Dual-path Loop-filter Technique FD-SOI Process Filter And Other Network Frequency 0.1 GHz to 6.4 GHz Frequency 21.25 MHz HDMI1.4 Host Clock Generation Jitter Loop-filter Capacitor Loop-filter Resistor Low Power Electronics Low-power System-on-chips Microwave IC Modulator Multiprotocol PLL Oscillator Output Jitter Reduction Phase Locked Loop Power 800 MuW Protocol Robust Jitter Performance Silicon-on-insulator Size 28 Nm System-on-chip Thermal Noise Time 14 Ps UHF Filter UHF Integrated Circuit USB2.0 Voltage-controlled Oscillator Wireline Standards
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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