NDLI: A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Content Provider	IEEE Xplore Digital Library
Author	Lahiri, A. Gupta, N. Kumar, A. Dhadda, P.
Copyright Year	1966
Abstract	This paper presents a 32 kHz input and 960 MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel dual-path loop-filter for resistor noise reduction technique. The resistor noise reduction technique using dual-path loop-filter involves no “additional” active component; area/power overhead compared to the conventional CP-PLL. Reverse sub-threshold leakage compensated source-switched charge-pump (SS-CP) is employed in the PLL for improved reference spur performance. The PLL with minimum analog supply voltage of 1.62 V and minimum digital supply voltage of 0.65 V; with die area of 0.15 mm ² is designed and fabricated in 28 nm STMicroelectronics FD-SOI process. The silicon measurement results have been included and the PLL performance includes total integrated jitter of 530 ps, reference spur of -65 dBc and current consumption of 600 μA.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1680
Ending Page	1689
Page Count	10
File Size	3290071
File Format	PDF
ISSN	00189200
Volume Number	50
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Resistors Voltage-controlled oscillators Noise Jitter Capacitors Charge pumps voltage-controlled oscillator (VCO) Charge-pump phase-locked loop (CP-PLL) jitter loop filter
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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