NDLI: PLL architecture with a composite PFD and variable loop filter

Content Provider	IET Digital Library
Author	K., Abdul Majeed K. Kailath, Binsu J.
Abstract	A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δ ϕ > π and provides a lower-gain and loop BW during tracking when Δ ϕ < π as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal–oxide–semiconductor process is found to achieve reference spur of −71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of −110 dBc/Hz at 100 kHz and final placement area of 0.244 m m 2 .
Starting Page	256
Ending Page	262
Page Count	7
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 3, May (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0336
Journal	IET Circuits, Devices & Systems
Publisher Date	2017-12-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Charge Pump Charge Pump Circuit Circuit Stability CMOS Analogue Integrated Circuit CMOS Integrated Circuit Complementary Metal-oxide-semiconductor Process Composite PFD Demodulator Discriminators And Mixers Filter And Other Network Frequency 100 KHz Frequency 2.56 GHz Frequency Measurement Microwave IC Microwave Measurement Technique Modulator Oscillator Phase And Gain Measurement Phase Detector Phase Frequency Detector Phase Locked Loop Phase Margin Equalization Phase Measurement Phase-locked Loop Architecture PLL Architecture Power Electronics Power Supply Sensing Device And Transducers Size 180 Nm Stability Supervisory Circuit Time 2.05 Mus Time 3.412 Ps UHF Detector UHF Filter UHF Integrated Circuit UHF Measurement UHF Oscillator Variable Loop Filter Topology Voltage-controlled Oscillator
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Spur reduction architecture for multiphase fractional PLLs

2.56 GHz sub-harmonically injection-locked PLL with cascaded DLL for multi-phase injection

Fast-locking PLL based on a novel PFD-CP structure and reconfigurable loop filter

Integer-N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Multi-band VCO PLL with continuously maintained optimum VCO control voltage

Injection-locked oscillator lock detector

A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs

Matrix phase detector for high bandwidth and low jitter frequency synthesis

Wide-range harmonic lock detector with real-time delay measurement of delay-locked loop

PLL architecture with a composite PFD and variable loop filter

Similar Documents

Spur reduction architecture for multiphase fractional PLLs

2.56 GHz sub-harmonically injection-locked PLL with cascaded DLL for multi-phase injection

Fast-locking PLL based on a novel PFD-CP structure and reconfigurable loop filter

Integer-N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Multi-band VCO PLL with continuously maintained optimum VCO control voltage

Injection-locked oscillator lock detector

A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs

Matrix phase detector for high bandwidth and low jitter frequency synthesis

Wide-range harmonic lock detector with real-time delay measurement of delay-locked loop

PLL architecture with a composite PFD and variable loop filter