NDLI: High performance DRAM architecture with split row buffer

Content Provider	IET Digital Library
Author	Lee, M. K. Chung, K. S.
Abstract	In dynamic random access memory (DRAM)-based main memory, access latency is a key performance metric. Commonly, the access latency is improved by employing row buffers that store the most recently accessed row data. However, if a new request tries to access a different row address from that in the row buffer, which is a row buffer conflict, the access latency is significantly increased. In a heterogeneous multi-core system, row buffer conflicts occur frequently because various types of processors with different access patterns share the main memory. A novel DRAM architecture that hides the latency penalty due to row buffer conflicts is proposed. The key idea is that read or write commands serviced during activate and precharge operations for different rows in the same bank are carried out by splitting the row buffer into two buffers. Experimental results show that the proposed DRAM architecture achieves up to 16% higher system performance for memory-intensive applications compared with a conventional DRAM architecture.
Starting Page	1844
Ending Page	1845
Page Count	2
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 22, Oct (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/22
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.1111
Journal	Electronics Letters
Publisher Date	2016-09-28
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Access Latency Improvement Activate Operations Buffer Storage DRAM Chips Dynamic Random Access Memory Heterogeneous Multicore System High Performance DRAM Architecture Latency Penalty Memory Architecture Memory Circuit Memory-intensive Application Multiprocessing System Performance Evaluation Performance Evaluation And Testing Performance Metrics Precharge Operation Read Command Semiconductor Storage Split Row Buffer Storage Requirements System Performance Write Command
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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