NDLI: Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Content Provider	IET Digital Library
Author	Jun, Jaehun Lee, Sangsu Kim, Chulwoo
Abstract	In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.
Starting Page	155
Ending Page	158
Page Count	4
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 2, Mar (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5468
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-10-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor AR Display System Augmented Reality Augmented Reality Display System CMOS Digital Integrated Circuit CMOS Integrated Circuit CMOS Technology Current 160.0 MuA Demodulator Digital Analogue Blocks Digital Phase Locked Loops Digital Phase-locked Loop Discriminators And Mixers DPLL Dynamic Voltage Range Electrical/electronic Equipment Energy Utilisation Forward Body Biasing Frequency 480.0 MHz Jitter Characteristic Low Power Electronics Low Voltage Optimised Digitally Controlled Oscillator Low-supply Voltage Modulator Near Threshold Voltage Digital PLL NTV Region Optimised Power Efficiency Oscillator Power Dissipation Sigma-delta Modulation Sigma-delta Modulator Block Size 65 Nm Time-digital Conversion Time-to-digital Converter Timing Jitter Ultra-low Power Consumption Virtual Reality Voltage 0.55 V Voltage-controlled Oscillator
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Near-threshold all-digital PLL with dynamic voltage scaling power management

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO

A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology

Analysis of the PLL jitter due to power/ground and substrate noise

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Similar Documents

Near-threshold all-digital PLL with dynamic voltage scaling power management

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO

A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology

Analysis of the PLL jitter due to power/ground and substrate noise

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system