NDLI: Half baud-rate, low BER PAM-4 CDR based on SS-MMSE algorithm

Content Provider	IET Digital Library
Author	Liu, Peng Guo, Jun Jiang, Yingtao
Abstract	A hardware-efficient four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR) circuit for high speed serial links is proposed, following a sign-sign minimum mean square error (SS-MMSE) algorithm. Using a specially designed continuous-sampling slope detector and a dual-stage digital filter, the proposed SS-MMSE CDR can align the clock phase well with the maximum vertical eye opening, as opposed to the conventional Bang-Bang CDR which only finds the midpoint of a symbol, yet requiring extra clock phases or running at higher frequency. Simulation results confirm superior performance and implementation efficiency of this proposed SS-MMSE PAM-4 CDR over the Bang-Bang design.
Starting Page	2036
Ending Page	2038
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 25, Dec (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/25
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.2944
Journal	Electronics Letters
Publisher Date	2016-11-21
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Clock And Data Recovery Circuit Continuous-sampling Slope Detector Conventional Bang-Bang CDR Digital Filter Dual-stage Digital Filter Error Statistics Four-level Pulse Amplitude Modulation Half-baud-rate PAM-4 CDR Hardware-efficient PAM-4 Clock And Data Recovery Circuit High-speed Serial Link Interpolation And Function Approximation Least Mean Squares Method Low-BER PAM-4 CDR Maximum Vertical Eye Opening Modulation And Coding Method Numerical Analysis Pulse Amplitude Modulation Sign-sign Minimum Mean Square Error Algorithm SS-MMSE Algorithm Statistics
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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