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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Silva, V. Fernandes, J.R. Vestias, M.P. Neto, H.C. |
| Copyright Year | 2012 |
| Description | Author affiliation: INESC-ID/ISEL/IPL, Lisbon, Portugal (Vestias, M.P.) || INESC-ID/IST/UTL, Lisbon, Portugal (Silva, V.; Fernandes, J.R.; Neto, H.C.) |
| Abstract | This paper presents a new architecture for a coarse-grained reconfigurable array targeted to linear algebra problems. The reconfiguration memories are implemented using magnetic tunneling junctions. These storage elements provide for non-volatility and for a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional mesh of double precision floating-point execution units. The execution units are run-time reconfigurable. Its configuration information defines the operation to be executed and the data flow intra and inter execution units. The synthesis results of a prototype design of a 4×4 array targeting a 65 nm CMOS technology confirm that the proposed architecture is able to provide a very significant computational density and that the magnetic-based configuration memory can provide a very area efficient run-time reconfigurability. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 538146 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467329194 |
| e-ISBN | 9781467329217 |
| DOI | 10.1109/ReConFig.2012.6416756 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-12-05 |
| Publisher Place | Mexico |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Context Ports (Computers) Double Precision Floating Point High-Performance Reconfigurable Computing Arrays Junctions Field programmable gate arrays Linear Algebra Magnetic tunneling Coarse Grain Reconfigurable Arrays |
| Content Type | Text |
| Resource Type | Article |
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