NDLI: Eight ways to put your FPGA on fire — A systematic study of heat generators

Content Provider	IEEE Xplore Digital Library
Author	Happe, M. Hangmann, H. Agne, A. Plessl, C.
Copyright Year	2012
Description	Author affiliation: Computer Engineering Group, University of Paderborn, Germany (Happe, M.; Hangmann, H.; Agne, A.; Plessl, C.)
Abstract	Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used. For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.
Starting Page	1
Ending Page	6
File Size	741790
Page Count	6
File Format	PDF
ISBN	9781467329194
e-ISBN	9781467329217
DOI	10.1109/ReConFig.2012.6416745
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-05
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	heat oscillator Pipelines FPGA Table lookup dedicated heat-generating core measurement Temperature measurement Heating Digital signal processing temperature Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA

An FPGA chip identification generator using configurable ring oscillator

Minimizing DSP block usage through multi-pumping

Iterative floating point computation using FPGA DSP blocks

Arithmetic core generation using bit heaps

Fast Hardware Computation of x Mod z

Eight ways to put your fpga on fire – a systematic study of heat generators.

Compact implementations of BLAKE-32 and BLAKE-64 on FPGA

Subthreshold capable, asynchronous FPGA in a 14nm SOI process

Eight ways to put your FPGA on fire — A systematic study of heat generators

Similar Documents

A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA

An FPGA chip identification generator using configurable ring oscillator

Minimizing DSP block usage through multi-pumping

Iterative floating point computation using FPGA DSP blocks

Arithmetic core generation using bit heaps

Fast Hardware Computation of x Mod z

Eight ways to put your fpga on fire – a systematic study of heat generators.

Compact implementations of BLAKE-32 and BLAKE-64 on FPGA

Subthreshold capable, asynchronous FPGA in a 14nm SOI process

Eight ways to put your FPGA on fire — A systematic study of heat generators