NDLI: Register file architecture optimization in a coarse-grained reconfigurable architecture

Content Provider	IEEE Xplore Digital Library
Author	Kwok, Z. Wilton, S.J.E.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada (Kwok, Z.; Wilton, S.J.E.)
Abstract	This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture. The register files consume a significant amount of area on the reconfigurable device, and their architecture has a strong impact on the performance. We found that the global registers should be tightly connected to as many functional units as possible, while the connection of the local register files to their neighbours is less critical. We found that the global register file should contain between 12 and 16 registers, while each local register file should only contain one or two registers. We used these results to propose a new architecture that has between 60% and 95% higher performance per unit area compared to the original architecture over the set of benchmarks.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on Comput. Archit
Starting Page	35
Ending Page	44
File Size	186128
Page Count	10
File Format	PDF
ISBN	0769524451
DOI	10.1109/FCCM.2005.58
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reconfigurable architectures Registers Computer architecture Random access memory Fabrics VLIW High performance computing Field programmable gate arrays Memory architecture Argon
Content Type	Text
Resource Type	Article

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