NDLI: MASH Δ-Σ DPWM based sliding-mode controller dedicating to high frequency SMPS

Content Provider	IEEE Xplore Digital Library
Author	Bo Li Shuibao Guo Xuefang Lin-Shi Allard, B.
Copyright Year	2011
Description	Author affiliation: Laboratoire AMPERE, UMR CNRS 5005, INSA de Lyon, Bât.Léonard de Vinci, 21, avenue Jean Capelle, Villeurbanne, France (Bo Li; Shuibao Guo; Xuefang Lin-Shi; Allard, B.)
Abstract	The high resolution digital pulse width modulator (DPWM) becomes a crucial part in digital controller for power converters that requires a fast system clock, especially applied to a high switching frequency SMPS. This paper proposes two solutions, the dithering Multi-stAge-noise-Shaping (MASH) and the 2–2 MASH delta-sigma (Δ-Σ) DPWM, so as to alleviate the inherent idle tone effects. An improved sliding mode controller (SMC) is also introduced here exhibiting better performance than the traditional PID compensator. Mixed-signal simulation are presented to demonstrate the theoretical analysis. Experimental results verify the SMPS close-loop operation on 3 V input with 5 V output, 1 A DC-DC boost converter at 1 MHz switching frequency, using a Virtex-II FPGA platform. A digital controller integrated chip (IC) including both DPWM and SMC is introduced as a verification prototype that potentially achieves switching frequency beyond 10MHz.
Starting Page	1
Ending Page	9
File Size	747476
Page Count	9
File Format	PDF
ISBN	9781612841670
e-ISBN	9789075815146
e-ISBN	9789075815153
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-30
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	EPE ASSOCIATION
Subject Keyword	Multi-stage noise shaping Digital control Frequency modulation Delta-sigma modulator Digital PWM Switching frequency Noise FPGA High frequency power converter Sliding mode control Clocks
Content Type	Text
Resource Type	Article

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