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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tao Li Yilei Wang Shengwen Tian Lan Lu |
| Copyright Year | 2008 |
| Description | Author affiliation: Network Center, Lu Dong Univ., Yantai (Tao Li) |
| Abstract | This paper first introduces automatic gating technology and its application on the CPU nucleus of Soc 1000 C. This paper puts forward a clock network design scheme that can exactly and credibly analyzes the sequence. It can reduce the SoC clock power dissipation without adding physical design complexity and also can improve the sequence capability and the CMOS chip unilateralist. At the end of this paper an experiment is given, the results of which illustrate that to qsort program the new method can reduce 35% power dissipation compared to traditional method and to Dijkstra program the new method can reduce 46% power dissipation compared to traditional method. |
| Starting Page | 2747 |
| Ending Page | 2750 |
| File Size | 199989 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424425020 |
| DOI | 10.1109/ICAL.2008.4636640 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-09-01 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Gating Clock CMOS SoC Logic gates Power dissipation Registers CMOS integrated circuits System-on-a-chip Synchronization Clocks |
| Content Type | Text |
| Resource Type | Article |
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