NDLI: A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors

Content Provider	IEEE Xplore Digital Library
Author	Stripf, T. Koenig, R. Becker, J.
Copyright Year	2011
Description	Author affiliation: Karlsruhe Institute of Technology, Karlsruhe, Germany (Stripf, T.; Koenig, R.; Becker, J.)
Abstract	Reconfigurable processor architectures can dynamically switch their instruction set and instruction format at run time. They offer a new flexibility for adapting to changing applications' requirements in order to optimize performance and enable resource-awareness. While programmability is a key issue of such architectures, today's software toolchains are limited to static ISA architectures and must be extended to support reconfigurable processors that can expose different ISAs at run time. In this paper, we address this shortcoming by presenting a novel retargetable software toolchain that is suitable for mixed-ISA application development as well as design space exploration (DSE). Therefore, we developed a novel mixed-ISA, compiler- and simulator-centric, behavioral architecture description language (ADL). The ADL provides the necessary flexibility to describe multiple ISAs for the software framework. The individual framework tools — the compiler, binary utilities, and instruction set simulator (ISS) — are generated from an ADL description. To realize the complex compiler inside the framework, we extended the LLVM compiler infrastructure by a mixed-ISA retargetable code generator (compiler back-end). To illustrate the flexibility of the ADL-based software toolchain, we performed a first DSE for application characterization of a variety of multi-domain applications. To show the feasible performance/resource benefits through dynamic reconfiguration, we further developed a mixed-ISA application that can dynamically change its instruction format at run time.
Starting Page	157
Ending Page	164
File Size	1353050
Page Count	8
File Format	PDF
ISBN	9781457708022
e-ISBN	9781457708015
DOI	10.1109/SAMOS.2011.6045457
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-18
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Computer architecture Encoding Hardware Registers Assembly
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files

Automatic Generation of Architecture Model for Reconfigurable Build Tools

Compiler framework for reconfigurable computing system

Extensible software emulator for reconfigurable instruction cell based processors

A LLVM based compiler for COFFEE

A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding

A Retargetable C Compiler for Embedded Systems

Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor

A restricted dynamically reconfigurable architecture for low power processors

A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors

Similar Documents

A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files

Automatic Generation of Architecture Model for Reconfigurable Build Tools

Compiler framework for reconfigurable computing system

Extensible software emulator for reconfigurable instruction cell based processors

A LLVM based compiler for COFFEE

A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding

A Retargetable C Compiler for Embedded Systems

Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor

A restricted dynamically reconfigurable architecture for low power processors

A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors