NDLI: Breaking the bandwidth wall in chip multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Vega, A. Cabarcas, F. Ramirez, A. Valero, M.
Copyright Year	2011
Description	Author affiliation: Barcelona Supercomputing Center and Universitat Politècnica de Catalunya (Vega, A.; Cabarcas, F.; Ramirez, A.; Valero, M.)
Abstract	In throughput-aware CMPs like GPUs and DSPs, software-managed streaming memory systems are an effective way to tolerate high latencies. E.g., the Cell/B.E. incorporates local memories, and data transfers to/from those memories are overlapped with computation using DMAs. In such designs, the latency of the memory system has little impact on performance; instead, memory bandwidth becomes critical. With the increase in the number of cores, conventional DRAMs no longer suffice to satisfy the bandwidth demand. Hence, recent throughput-aware CMPs adopted caches to filter off-chip traffic. However, such caches are optimized for latency, not bandwidth. This work presents a re-design of the memory system in throughput-aware CMPs. Instead of a traditional latency-aware cache, we propose to spread the address space using fine-grained interleaving all over a shared non-coherent last-level cache (LLC). In this way, on-chip storage is optimally used, with no need to keep coherency. On the memory side, we also propose the use of interleaving across DRAMs but with a much finer granularity than usual page-size approaches. Our proposal is highly optimized for bandwidth, not latency, by avoiding data replication in the LLC and by using fine-grained address space interleaving in both the LLC and the memory. For a CMP with 128 cores and 64-MB LLC, performance is improved by 21% due to the LLC optimizations and an extra 42% due to the off-chip memory optimizations, for a total 1.7 times performance improvement.
Starting Page	255
Ending Page	262
File Size	1268669
Page Count	8
File Format	PDF
ISBN	9781457708022
e-ISBN	9781457708015
DOI	10.1109/SAMOS.2011.6045469
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-18
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Random access memory Bandwidth Computer architecture Coherence Organizations Proposals
Content Type	Text
Resource Type	Article

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