NDLI: Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Gohringer, D. Oey, O. Hubner, M. Becker, J.
Copyright Year	2011
Description	Author affiliation: ITIV, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany (Hubner, M.; Becker, J.) \|\| Fraunhofer IOSB, Ettlingen, Germany (Gohringer, D.; Oey, O.)
Abstract	Multiprocessor Systems-on-Chip (MPSoCs) are a promising solution to fulfill the requirements of high performance computing applications, such as image processing or bioinformatics. Many different MPSoC architectures are introduced by industry and academics, such as Intel's Single Cloud Computer (SCC) or IBM's Cell. To achieve a high efficiency on such MPSoCs a high computing performance in the processing elements (PE) is not the only parameter. The bandwidth of the memory and especially the on-chip communication infrastructure are extremely important to achieve the requirements of the applications. Furthermore, for embedded System-on-Chip solutions, flexibility is extremely important for providing a good tradeoff between performance and power consumption. Especially, for general purpose MPSoCs, designed for a wide range of applications with different communication demands, this flexibility is essential for a good energy efficiency. A simple bus or Network-on-Chip (NoC) with fixed bandwidth and communication paradigm is not sufficient in this varying application scenario and its design space. In this paper novel features for the heterogeneous and runtime adaptive Star-Wheels Network-on-Chip are presented. This Network-on-Chip is used within a runtime adaptive MPSoC, which enables to tailor processors and accelerators to the requirements of the applications. For optimizing the Star-Wheels Network-on-Chip and its communication protocol at runtime to the application requirement the following novel features have been added: the combination of the circuit- and the packet-switched communication paradigm and an algorithm-based placement of the processing elements within the NoC. The integration of the novel algorithm into the design methodology and the exploitation of the novel features within the special purpose runtime operating system of a runtime adaptive MPSoC are also introduced.
Starting Page	380
Ending Page	387
File Size	1807778
Page Count	8
File Format	PDF
ISBN	9781457708022
e-ISBN	9781457708015
DOI	10.1109/SAMOS.2011.6045488
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-18
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Protocols Dynamic and Partial Reconfiguration FPGA Switches Receivers Network-on-Chip (NoC) Task allocation Routing Multiprocessor System-on-Chip (MPSoC) Topology Switching circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol

FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications

Efficient run-time task allocation in reconfigurable multiprocessor System-on-Chip with Network-on-Chip

Adaptive routing scheme for NoC communication architecture

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework

Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim

Parameterizable Ethernet Network-on-Chip Architecture on FPGA

Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC

Déjà Vu Switching for Multiplane NoCs

Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip

Similar Documents

Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol

FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications

Efficient run-time task allocation in reconfigurable multiprocessor System-on-Chip with Network-on-Chip

Adaptive routing scheme for NoC communication architecture

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework

Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim

Parameterizable Ethernet Network-on-Chip Architecture on FPGA

Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC

Déjà Vu Switching for Multiplane NoCs

Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip