NDLI: ADL-based specification of implementation styles for functional simulators

Content Provider	IEEE Xplore Digital Library
Author	Penry, D.A. Cahill, K.D.
Copyright Year	2011
Description	Author affiliation: Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA (Penry, D.A.; Cahill, K.D.)
Abstract	Functional simulators find widespread use as sub-systems within microarchitectural simulators. The speed of functional simulators is strongly influenced by the implementation style of the functional simulator, e.g. interpreted vs. binary-translated simulation. Speed is also strongly influenced by the level of detail of the interface the functional simulator presents to the rest of the timing simulator. This level of detail may change during design space exploration, requiring corresponding changes to the interface and the simulator. However, for many implementation styles, changing the interface is difficult. As a result, architects may choose either implementation styles which are more malleable or interfaces with more detail than is necessary. In either case, simulation speed is traded for simulator design time. We show that this tradeoff is unnecessary if an orthogonal-specification design principle is practiced: specify how a simulator is to be implemented separately from what it is implementing and then synthesize a simulator from the combined specifications. We show that the use of an Architectural Description Language (ADL) with constructs for implementation style specification makes it possible to synthesize interfaces with different implementation styles with reasonable effort.
Starting Page	165
Ending Page	173
File Size	1268038
Page Count	9
File Format	PDF
ISBN	9781457708022
e-ISBN	9781457708015
DOI	10.1109/SAMOS.2011.6045458
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-18
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microarchitecture Semantics Organizations Generators Timing Decoding Space exploration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A single-specification principle for functional-to-timing simulator interface design

An ADL for Functional Specification of IA32

ADL-Based Specification of Implementation Styles for Functional Simulators

Executable specification for multimedia supporting refinement and architecture exploration

Automatic Generation of Microarchitecture Simulators (1998)

Validation of Turandot, a fast processor model for microarchitecture exploration

Automatic Generation of Microarchitecture Simulators (1998)

Functional abstraction driven design space exploration of heterogeneous programmable architectures

A versatile generator of instruction set simulators and disassemblers

ADL-based specification of implementation styles for functional simulators

Similar Documents

A single-specification principle for functional-to-timing simulator interface design

An ADL for Functional Specification of IA32

ADL-Based Specification of Implementation Styles for Functional Simulators

Executable specification for multimedia supporting refinement and architecture exploration

Automatic Generation of Microarchitecture Simulators (1998)

Validation of Turandot, a fast processor model for microarchitecture exploration

Automatic Generation of Microarchitecture Simulators (1998)

Functional abstraction driven design space exploration of heterogeneous programmable architectures

A versatile generator of instruction set simulators and disassemblers

ADL-based specification of implementation styles for functional simulators