NDLI: Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips

Content Provider	IEEE Xplore Digital Library
Author	Collet, J.H. Psarakis, M. Zajac, P. Gizopoulos, D. Napieralski, A.
Copyright Year	2009
Description	Author affiliation: Department of Microelectronics and Computer Science, Technical University of Lodz, ul. Wólcza¿ska 221/223, 90-924, Poland (Napieralski, A.) \|\| Computer Systems Laboratory, Department of Informatics, University of Piraeus, 80 Karaoli & Dimitriou Street, 18534 Piraeus, Greece (Psarakis, M.; Gizopoulos, D.) \|\| Laboratoire d'Analyse et d'Architecture des Systèmes du CNRS, 7 avenue du colonel Roche, Université de Toulouse, 31077, France (Collet, J.H.; Zajac, P.)
Abstract	The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches, which are based on chip self-diagnosis and self-reconfiguration. We study test and reconfiguration methodologies in massively defective nanoscale devices, either at fine granularity field programmable devices or at coarse granularity multi-core arrays. In particular, we address the important question of up to which point could future chips have self-organizing fault-tolerance mechanisms to autonomously ensure their own dependable operation. In the case of FPGAs, we present known fault tolerant approaches and discuss their limitations in future nanoscale devices. In the case of multicore arrays, we show that such properties as self-diagnosis, self-isolation of faulty elements and self-reorganization of communication routes are possible.
Starting Page	23
Ending Page	30
File Size	172018
Page Count	8
File Format	PDF
ISBN	9781424447985
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-25
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz
Subject Keyword	Multicore processing fault tolerance Redundancy FPGA testing diagnosis reconfiguration Circuit faults Circuit testing Phased arrays Fault tolerance multicore architectures CMOS technology Nanoscale devices Protection Field programmable gate arrays Nanotechnology
Content Type	Text
Resource Type	Article

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