NDLI: Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors

Content Provider	IEEE Xplore Digital Library
Author	Zydek, D. Selvaraj, H. Gewali, L.
Copyright Year	2010
Abstract	Chip MultiProcessor (CMP) architectures are dominant trend in parallel processing systems. With the number of on-chip processors rising to the hundreds, allocation and management of the processors are also important factor to achieve high efficiency of CMPs. In this paper, the authors study a Processor Allocator (PA) for CMP based on torus Network-on-Chip. The best, IFF and IAS algorithms for mesh-based CMP are presented and their torus extension is proposed. The synthesis of both IFF and IAS allocation techniques for mesh and torus topologies is performed and its results are analyzed. The presented outcomes reveal the significant advantage of the PA driven by bit map algorithms. The mesh-based PA driven by the IFF scheme outperformed the other techniques by good frequency characteristic and low logic utilization. For the torus-based PA only the IFF technique with torus extension remains the reasonable solution, however its performance characteristic is weaker in comparison to the mesh counterpart.
Starting Page	13
Ending Page	18
File Size	350273
Page Count	6
File Format	PDF
ISBN	9781424462704
e-ISBN	9781424462711
DOI	10.1109/ITNG.2010.145
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption torus NoC FPGA CMP Throughput Information technology Network topology Processor scheduling Network-on-a-chip Parallel processing processor allocator Network synthesis Resource management System-on-a-chip mesh hardware implementation
Content Type	Text
Resource Type	Article

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