NDLI: Simulated power analysis attacks on a DDPL crypto-core without routing constraints

Content Provider	IEEE Xplore Digital Library
Author	Bongiovanni, S. Scotti, G. Trifiletti, A.
Copyright Year	2013
Description	Author affiliation: Dipt. di Ing. dell'Inf., Elettron. e Telecomun. (DIET), Univ. degli Studi di Roma La Sapienza, Rome, Italy (Bongiovanni, S.; Scotti, G.; Trifiletti, A.)
Abstract	Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which allows to design a PA-resistant circuit without routing constraints. In this work we present a fair comparison between SABL, a well-known state of the art transistor level countermeasure which is sensitive to the capacitive mismatches on the complementary lines and requires a customized routing procedure, and DDPL. After having provided a power model for describing the leakage sources for the above mentioned logics, a simple cryptographic circuit has been designed for both SABL and DDPL, and a CPA attack has been mounted. Simulations results show that when capacitive load unbalances are considered, DDPL strongly outperforms SABL in terms of number of traces required for disclose the secret key.
Starting Page	345
Ending Page	348
File Size	301479
Page Count	4
File Format	PDF
ISBN	9781467345804
e-ISBN	9781467345811
DOI	10.1109/PRIME.2013.6603185
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-24
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Sense Amplifier Based Logic (SABL) Correlation Power Analysis (CPA) Logic gates Routing Capacitance Cryptography Delay-based Dual-rail Pre-charge Logic (DDPL) Dual-rail Pre-charge Logic (DPL) Clocks Load modeling
Content Type	Text
Resource Type	Article

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