NDLI: A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family

Content Provider	IEEE Xplore Digital Library
Author	Bongiovanni, S. Olivieri, M. Scotti, G. Trifiletti, A.
Copyright Year	2013
Description	Author affiliation: DIET, Univ. degli Studi di Roma “La Sapienza”, Rome, Italy (Bongiovanni, S.; Olivieri, M.; Scotti, G.; Trifiletti, A.)
Abstract	Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is breaking the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave flip-flop which is compatible with the DDPL data encoding. Efforts were made in order to design a fully dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover it will be shown that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performances in terms of average power and NED (Normalized Energy Deviation) as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions.
Starting Page	163
Ending Page	168
File Size	1711574
Page Count	6
File Format	PDF
e-ISBN	9788363578022
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-20
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Department of Microelectronics and Computer Science, Technical University of Lodz
Subject Keyword	Power demand Latches delay-based dual-rail pre-charge logic (DDPL) power analysis (PA) Master-slave sense amplifier-based logic (SABL) Inverters VLSI design Flip-flops Logic gates dynamic flip-flop Cryptography dual-rail logic Clocks
Content Type	Text
Resource Type	Article

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