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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Runchun Wang Thakur, C.S. Hamilton, T.J. Tapson, J. van Schaik, A. |
| Copyright Year | 2015 |
| Description | Author affiliation: MARCS Inst., Univ. of Western Sydney, Sydney, NSW, Australia (Runchun Wang; Thakur, C.S.; Hamilton, T.J.; Tapson, J.; van Schaik, A.) |
| Abstract | We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order low-pass filters to implement a conductance-based silicon neuron for high-speed neuromorphic systems. The aVLSI neuron consists of a soma (cell body) and a single synapse, which is capable of linearly summing both the excitatory and inhibitory post-synaptic potentials (EPSP and IPSP) generated by the spikes arriving from different sources. Rather than biasing the silicon neuron with different parameters for different spiking patterns, as is typically done, we provide digital control signals, generated by an FPGA, to the silicon neuron to obtain different spiking behaviours. The proposed neuron is only ~26.5 $μm^{2}$ in the IBM 130nm process and thus can be integrated at very high density. Circuit simulations show that this neuron can emulate different spiking behaviours observed in biological neurons. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1411985 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781479972340 |
| DOI | 10.1109/BioCAS.2015.7348396 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-10-22 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Neurons Logic gates Silicon Transistors Integrated circuit modeling Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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